Php – TYPO3 Extbase Controller/Model Validation fails

Here's a modified version of one of my pet projects. It should do exactly as you wanted: display 4 3 2 1 on the 4dig7seg display. I tested it on an Amani GTX CPLD, and it should transfer cleanly to your board.

I like separating projects into separate modules to keep organized. The top level module takes the on board clock as an input and outputs 14 signals to a four-digit-seven-segment serial display. Make sure the pins are correctly assigned.

module SevenSeg(clk, odig, onum, col, ap); 

input clk;         // 50 MHz oscillator 
output [3:0] odig; // selected digit output
output [7:0] onum; // selected display output
output col = 1;    // turns the colon off 
output ap  = 1;    // turns the apostrophe off 

wire clock;        // divided oscillator to slow the display output 

parameter a   = 8'b11111110; // low means on, high means off  
parameter b   = 8'b11111101; // these are just parameters  
parameter c   = 8'b11111011; // defining each of the 
parameter d   = 8'b11110111; // seven segments 
parameter e   = 8'b11101111; // making life easier
parameter f   = 8'b11011111; 
parameter g   = 8'b10111111; 
parameter dp  = 8'b01111111; 

parameter off = 8'b11111111; 

parameter one    =  b & c;             // parameters for outputs
parameter two    =  a & b & d & e & g; 
parameter three  =  a & b & c & d & g; 
parameter four   =  b & c & f & g; 


    wire [7:0] port1 = one;   // This is set up so these can change dynamically...
    wire [7:0] port2 = two;   // ... if so desired.     
    wire [7:0] port3 = three;
    wire [7:0] port4 = four;


slowclk m1(clk, clock);   // divides clk by 500, for 50 MHz in, 100 kHz out 

digitize m2(clock, port1, port2, port3, port4, odig, onum); // rotates the digit outputs 

endmodule 

Next I have a simple clock divider. The case count = 500 can be modified to divide your clock to whatever frequency you like. The output should look fine in the range of about 120 Hz to about 2 MHz.

module slowclk(clk, clock); 

input clk; 
output reg clock; 
integer count; 

always @(posedge clk) 
case(count)      
500: begin clock <= clock + 1; count <= 0; end   // Change 500 to any divisor you like
default:  count <= count + 1;   
endcase 
endmodule   

Then we have to rotate the digits. Note if you change the anodes and cathodes at the "same" time, there will be a small leakage current into the neighboring segments causing a "ghost" effect.

module digitize(clock, num1, num2, num3, num4, odig, onum); 

input wire clock; 
input [7:0] num1; // rightmost digit 
input [7:0] num2; 
input [7:0] num3; 
input [7:0] num4; // leftmost digit 

output reg [3:0] odig; 
output reg [7:0] onum; 

parameter [7:0] off = 8'b11111111; 

reg [3:0] dstate; 

always @(posedge clock) 
case(dstate) 
0:begin   odig   <= 4'b0001; dstate <=  1; end 
1:begin   onum   <= num1;    dstate <=  2; end 
2:begin   onum   <= off;     dstate <=  3; end  // off states prevent 'ghosting' 
3:begin   odig   <= 4'b0010; dstate <=  4; end  // when changing output digit 
4:begin   onum   <= num2;    dstate <=  5; end 
5:begin   onum   <= off;     dstate <=  6; end 
6:begin   odig   <= 4'b0100; dstate <=  7; end 
7:begin   onum   <= num3;    dstate <=  8; end 
8:begin   onum   <= off;     dstate <=  9; end 
9:begin   odig   <= 4'b1000; dstate <= 10; end 
10:begin  onum   <= num4;    dstate <= 11; end 
11:begin  onum   <= off;     dstate <=  0; end 
default:  dstate <= 0; 
endcase 
endmodule 

Use a temporary variable, and multiply each item to it:

def product_list(my_list):  # Don't use `list` as variable name
    product = 1
    for item in my_list:
        product *= item
    return product

A better way would be to use reduce() with operator.mul:

import operator

def product_list(my_list):
    return reduce(operator.mul, my_list, 1)