Verilog always block statement

verilog

i just want to know the difference between this two statement 

always @(posedge CLK)
    begin
       state <= next_state;
    end

AND:

always @(CLK)
    begin
     case(CLK)
        1'b1:
           state <= next_state;
        1'b0:
           state <= state;
    end

Is there a difference between both ?

Thanks

Best Answer

Not quite. posedge detects these transitions (from the LRM):

Table 43—Detecting posedge and negedge
To   0       1       x       z
From
0    No edge posedge posedge posedge
1    negedge No edge negedge negedge
x    negedge posedge No edge No edge
z    negedge posedge No edge No edge

So, 0->x is a posedge, for example. Your second example only detects cases where CLK ends up as 1, so misses 0->x and 0->z.

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