VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)

If you want the length of an integer as in the number of digits in the integer, you can always convert it to string like str(133) and find its length like len(str(123)).

Firstly, full marks for avoiding not use std_logic_arith!

If you define your vectors as unsigned then (outside of a process) all that is required is this:

  cn_plus_1 <= not cn when cn < halfc else (not cn) + 1;

and you can assign cn_plus_1 to a std_logic_vector thus:

wCntReg <= std_logic_vector(cn_plus_1);

Here's a couple of complete examples of VHDL idiomatic ways of doing it:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity funny_counter1 is
    port (
        cn: IN unsigned(15 downto 0);
        cn_plus_1 : out unsigned(15 downto 0));
end entity funny_counter1;

architecture a1 of funny_counter1 is
    constant halfc : unsigned(cn'range) := (cn'high => '1', others => '0');
begin  -- architecture a1
    cn_plus_1 <= not cn when cn < halfc else (not cn) + 1;
end architecture a1;

or in a synchronous process:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity funny_counter is
    port (
        clk   : in  std_logic;
        reset : in  std_logic;
        cout  : out unsigned(15 downto 0));
end entity funny_counter;

architecture a1 of funny_counter is
    constant halfc : unsigned(cout'range) := (cout'high => '1', others => '0');
begin
    process (clk) is
        variable c   : unsigned(15 downto 0);
        variable add : integer range 0 to 1;
    begin  -- process
        if rising_edge(clk) then  -- rising clock edge
            if reset = '1' then
                c := (others => '0');
            else
                add := 0;
                if c < halfc then
                    add := 1;
                end if;
                c := (not c) + add;
            end if;
            cout <= c;
        end if;
    end process;
end architecture a1;

Whenever you find yourself converting a lot between std_logic_vectors and integers (or similar), you are usually working with actual numbers. Work with either unsigned/signed vectors or with integers. If you need a vector at the end of it all, convert it one and for all at the end. It's not pleasant to look at necessarily. But first ask if the thing you are sending the value to ought to be using a numerical type of some sort on its interface. Only if it truly is a 'bag-of-bits' is a std_logic_vector the best type. The name wCntReg sound like a count value to me, so it should have a numeric type to my mind.

This code you have:

wCntReg <= std_logic_vector(to_unsigned(natural'pos(tmp_na), wCntReg'length));

is slightly worse than it needs to be:

wCntReg <= std_logic_vector(to_unsigned(tmp_na, wCntReg'length));

ought to work fine.

Finally, you comment on this only coming into effect on the next clock tick is how VHDL works - signals are only updated when some time passes (often this is only at the end of a process). If you want to make use of the new value before then, use a variable - they update straight away.

So if your tempna were a variable, you could do the wCntReg assignment straight after.

For completeness: another way around this (which is usually a kludge IME) is to wait for 0 ns; after the signal assignment. This causes some time to pass from the point of view of updates, so all other delta cycles will execute for the current time (including the signal assignment you want to propgate) time will move on (by 0ns!) and a new delta cycle can begin.