Verilog Error: output or inout port “Q” must be connected to a structural net expression

I keep getting the error everytime i try to compile i'm not sure why. Can anyone help? I'm new to verilog.

module D_FF(Clk, D, Reset_n, Q);

    input D, Clk, Reset_n;
    output Q;
    reg Q;

    lab4_GDL f1(.Clk(~Clk), .D(D), .Q(Qm));

    lab4_GDL f2(.Clk(Clk), .D(Qm), .Q(Q));

    always @(posedge Clk, negedge Reset_n)
    begin
        if (Reset_n == 0)
            Q <= 0;
        else
            Q <= D;

    end
endmodule

EDIT: This is what the problem was asking us to do:

In this part, you will implement a memory / register circuit on the AlteraDE2 board. The circuit has the following specifications:

1. The current value of switches SW15-0 on the DE2 board should always be displayed in hexadecimal on the four seven-segment displays HEX3-0. This part of the circuit will be combinational logic.

2. Using KEY0 as an active-low asynchronous reset and KEY1 as a clock input, you should be able to store the value on SW15-0in a 16-bit register. The register should be a 16-bit positive edge triggered register that uses the embedded D flip-flops in the Altera FPGA.
   You can either instantiate D flip-flops or write a behavioral Verilog model for your register. The contents of this register should always be displayed on the four seven-segment displays HEX7-4.

Write a Verilog file that provides the necessary functionality. Use KEY0 as an active-low asynchronous reset, and use KEY1 as a clock input. You should be able to re-use your hex-to-7 segment display module from the last lab. When reset is pressed HEX7-4 will display all zero's.

This the last lab it is referring too:

module updown (SW, KEY, LEDR, LEDG, GPIO_0, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);
parameter n=32;     // number of bits in updown counter
input [0:0] SW;     // Updown switch 1=up, 0=down
input [0:0] KEY;    // KEY[1] = Clock, KEY[0] = Reset_n
input [0:0] GPIO_0; 
output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
output [n-1:0] LEDR;    // Display binary count (active high) on Red LEDs
output [1:0] LEDG;  // Display Clock on LEDG[1], Reset_n on LEDG[0]
wire Clock, Reset_n, Updown;
reg [n-1:0] Count;

assign Clock = GPIO_0[0];
assign Reset_n = KEY[0];
assign Updown = SW[0];
assign LEDR = Count;
assign LEDG[1:0] = {Clock, Reset_n};

always @(posedge Clk, negedge Reset_n) //clock = Clk
    if (Reset_n == 0)       // active-low asynchronous reset
        Q <= 0;
    else        
        Q <= D; 

My lab4_GDL is the following:

// A gated RS latch
module lab4_GDL(Clk, D, Q);
    input Clk, D;
    output Q;

    wire R_g, S_g, Qa, Qb /* synthesis keep */;
    assign R = ~D;
    assign R_g = ~(R & Clk);
    assign S_g = ~(D & Clk);
    assign Qb = ~(R_g & Qa);
    assign Qa = ~(S_g & Qb);

    assign Q = Qa;

endmodule