Vhdl Type mismatch error

vhdl

I am having a type mismatch error, but all values are of same type std_logic.
Here is the code

Nx, Ny – generics

ipx – an input port vector

tempx, tempz – signals

ipx : in std_logic_vector(Nx-1 downto 0);
…….
signal tempx : std_logic_vector(Ny-1 downto 0) := ipx(Nx-1 downto Nx-Ny); (Signal initialisation)
signal tempz : std_logic_vector(Ny-1 downto 0);
…………
tempx <= (Ny-1 downto 1 => tempz(Ny-2 downto 0), 0 => ipx(a-1));

error : Error (10381): VHDL Type Mismatch error at ArrayDivider.vhd(53): indexed name returns a value whose type does not match "std_ulogic", the type of the target expression
(Error on last code line of tempx)

But ipx and tempz both are std_logic vectors so, where is the type mismatch here????
Please give me some solution

I have tried on using the concatenate operator & also but it gives me another error related to top level hierarchy and 'can't resolve multiple constant drivers of tempx[0]' !!!!!!

Best Answer

The error message tells you exactly what the problem is:

error : Error (10381): VHDL Type Mismatch error at ArrayDivider.vhd(53): indexed name returns a value whose type does not match "std_ulogic", the type of the target expression

And indeed, tempz(Ny-2 downto 0) is not a std_ulogic but a vector.

The problem is that named association does not identify slices of a vector but individual elements; you can't use it to assign one slice of one vector to a slice of another vector.

Instead, use the concatenation operator &,

tempx <= tempz(Ny-2 downto 0) & ipx(a-1);

Your post implies that concatenation produces other errors; feel free to add these to the question.

EDIT :

>Error (10028): Can't resolve multiple constant drivers for net 
>"tempx[0]" at ArrayDivider.vhd(44) (on the line of initialing >tempx)

Again this tells you what is wrong. This error is almost certainly there in both versions of the design, but the original error just hides it. Find the two drivers for tempx(0) and eliminate whichever is the wrong one. You haven't posted enough of your code to make it clear what's going on so that is up to you. If you're using Modelsim, the "drivers" command will identify all the drivers on a signal.

If you need to initialise tempx to the input signal and then later drive it with another signal, you must select between the two signals - for example:

tempx <= ipx(Nx-1 downto Nx-Ny) when <some condition>
         else tempz(Ny-2 downto 0) & ipx(a-1);

Most likely, fixing this error will also eliminate the "hierarchy" error; which is basically "something went wrong earlier so compilation cannot be completed".

Related Solutions

Can’t resolve multiple constant drivers VHDL Error

The error is telling you that you have multiple drivers on tempx[0].

In the code you posted, there is only one conditional assignment to tempx.

However it is embedded in a for ... generate statement.

That means you are probably generating multiple copies of it, depending on the values of nx,ny. Hence the error.

EDIT

It doesn't help that you are posting an unreadably small picture instead of actual VHDL code. Please edit the question with your code.

Meanwhile I think I can see that you are generating a set of different modules (Cmp?) and feeding a different input signal to each.

However you cannot drive all these signals on the same signal at the same time! That is what the tools are telling you. What you need is an array of signals, indexed by the generate variable, a.

subtype temp is std_logic_vector(N downto 0);
signal Tempx : array(Nx-Ny downto 0) of temp;
...

for a in ... generate
   tempx(a) <= (whatever expression you have now);
   Cmpa : generic map (...) port map (tempx(a), ...);
end generate;

Now, obviously, each member of the array has only one driver, eliminating the multiple driver errors.

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Leading zero's on numbers indicate octal format. Octal only goes up to 7, so 08 wouldn't be valid.

Best Answer

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Can’t resolve multiple constant drivers VHDL Error

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