What’s included in a verilog always @* sensitivity list

digital-logicverilog

I'm a bit confused about what is considered an input when you use the wildcard @* in an always block sensitivity list. For instance, in the following example which signals are interpreted as inputs that cause the always block to be reevaluated? From what I understand clk and reset aren't included because they dont appear on the right hand side of any procedural statement in the always block. a and b are included because they both appear on the right hand side of procedural statements in the always block. But where I'm really confused about is en and mux. Because they are used as test conditions in the if and case statements are they considered inputs? Is the always block reevaluated each time en and mux change value? I'm pretty much a noob, and in the 3 Verilog books I have I haven't found a satisfactory explanation. I've always found the explanations here to be really helpful. Thanks

module example
( 
    input wire clk, reset, en, a, b,
    input wire [1:0] mux,
    output reg x,y, z
);

always @*    
begin  
 x = a & b;    
  if (en)
    y= a | b;
  case(mux)
    2'b00: z = 0;
    2'b01: z = 1;
    2'b10: z = 1;
    2'b11: z = 0;
  endcase
end
endmodule

Best Answer

Any signal that is read inside a block, and so may cause the result of a block to change if it's value changes, will be included by @*. Any change on a read signal used must cause the block to be re-evaluated, as it could cause the outputs of the block to change. As I'm sure you know, if you hadn't used @* you'd be listing those signals out by hand.

In the case of the code you've provided it's any signal that is:

Evaluated on the right hand side of an assignment (a and b)
Evaluated as part of a conditional (en and mux)

...but it's any signal that would be evaluated for any reason. (I can't think of any other reasons right now, but maybe someone else can)

clk and reset aren't on the sensitivity list because they aren't used. Simple as that. There's nothing special about them; they're signals like any other.

Related Solutions

Verilog – always sensitivity list

Unless you're modelling a clocked flip flop, you should always use the default (@*) sensitivity list for a combinational block. There's no synthesizable combinational circuit which is only sensitive to the negative edge of a signal.

If you really want to do something only when a key is initially pressed, then compare the key state to the value of the key from the previous clock edge stored in a register.

always @* begin
  if(key[0] && !key_last[0]) begin
      //assert some signal on key0 press
  end
  if(key[1] ...) begin
      //assert on key1 press
  end
end

always @(posedge clock) key_last <= key;

If you intend to check the state of more than one key, then you shouldn't use if/else statement, as that will stop checking after the first true statement. Just write four individual if statements.

Mixing blocking and non-blocking assign in Verilog (or not!)

When using the blocking (=) assignment the value is available to use in the next line of code. This implies it is combinatorial and not driven from a flip-flop.

In simulation it looks like it is driven from a flip-flop because the block is only evaluated on positive clock edge, in reality it is not which might break the interface.

I am of the faction which says never mix styles, as it can be a problem in code reviews and refactoring. The refactor, if a module needs to output a new signal and it is seen that it already exists they just change to be an output. At first glance looked like it was a flip-flop because it was in a always @(posedge clk block.

Therefore I would recommend to NOT mix styles, but pull out the section that is combinatorial and put it in its own block. Does this still meet your requirements? if not then you would have had problem.

I do not see how data valid is controlled but it can change the output transmitting, potentially transmitting could also glitch as it is from a combinatorial decode, not driven cleanly from a flip-flop. The receiving interface might be async, glitches could cause lock up etc.

always @* begin
  if(shiftIndex == 0) begin
    if(dataValid == 1) transmitting = 1; //Blocking assign
    else transmitting = 0; //Blocking assign
  end
end

always @ (posedge clk) begin
  if(transmitting == 1) begin
    shiftIndex <= shiftIndex + 1;
    dataOut    <= data5b[shiftIndex];

   if(shiftIndex == 4) begin
       complete   <= 1;
       shiftIndex <= 0;
   end
   else begin
       complete   <= 0;
   end
  end
end

Best Answer

Related Solutions

Verilog – always sensitivity list

Mixing blocking and non-blocking assign in Verilog (or not!)

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