I have tried to make a counter which counts until six clock cycles and then repeats.
And would like to know whether I have done all right and the counter works correct.
simulate this circuit – Schematic created using CircuitLab
3 – bit Counter (repeat after each 6 clocks)
counterdigital-logic
Related Solutions
At first glance, this appears to be a power problem. It appears that your "5 V" power supply droops to less than 4 V in operation.
Perhaps the power supply is inadequate. So power your circuit from some other wall-wart or other power supply that can supply at least 10 times as much power as you think you need (at least 10 times as much current at 5V). (Another possible explanation: perhaps the wires and connectors and traces between your power supply and the chip's GND and power pins have too much resistance; so replace them with thicker wires and less oxidized connectors).
No matter how good the wall-wart is, it can't do anything about the inductance in the wires between the wall-wart and your PCB. That inductance creates an impedance significantly larger than measuring the resistance of those wires might suggest. You need a "bulk capacitance" capacitor on your board. There are ways to calculate how much you need, but many people just throw on a 1000 uF capacitor on their first prototype -- usually overkill, but not worth trying to find out how much less we actually "need". "Logic Supply Decoupling Techniques", "General PCB Design Guide", "Decoupling Capacitance Design Rules", "Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology", etc.
No matter how good a bulk capacitor is, it can't do anything about the inductance in the traces between that capacitor and each IC. That inductance creates an impedance significantly larger than measuring the resistance of those traces might suggest. Put a 100nF decoupling capacitor across the GND and power pin of every IC. "Decoupling Capacitors Explained -or- If You Like It Then You Shouldn’t Let It Ring Like That", "What is a decoupling capacitor and how do I know if I need one?", "Decoupling by Example", etc.
Unfortunately, these 3 problems bite extremely often, and cause all kinds of strange and not-quite-working-right behaviors.
(How do we add "decoupling and bulk capacitance" to the Electrical Engineering site FAQ ?)
While @optronik's answer is one method of doing it, and the one which uses the least amount of hardware, it's not the best approach.
The issue is one of propagation delays. If you use the MSB of counter 1 as a clock for counter 2 what will happen is there will be a delay between the count values.
When the clock signal for counter 1 triggers it to overflow (go from 15 to 0), there will be a small delay between that clock edge and counter 1's output updating. Once the output has updated, counter 2 will be clocked, but again there will be a delay in its output updating. So counter 1 will change its output \$t_p\$ seconds after the clock, but counter 2 won't change until \$2\times t_p\$ seconds after the clock.
This could cause glitches in whatever the counter output is connected too - the problem will become more apparent the more counters you used. This is why we design synchronous counters instead of ripple counters.
There are synchronous solutions to the issue.
If your counters are ICs - i.e. not something you have wired up from logic gates - you can make the second counter synchronous with the first by using the same clock for both counters (not the MSB of counter 1).
a) if the counter has an enable pin, connect the enable of counter 2 the bitwise AND of all bits of counter 1 (i.e. a 4-input AND gate). Connect the clock signal to the clock pin of the counter 2.
b) If there is no enable pin, you need a 5-input AND gate. Connect four inputs to counter 1 and the fifth goes to the clock signal. The output of the AND gate goes to the clock pin of counter 2. There will be a small propagation delay added, but it won't add up if you cascade more timers.
I should note that the (b) approach requires a negative-edge clock signal to work correctly. If you have a positive edge triggered flip-flop, you can still use this approach, but instead of a 5-input AND, you need a 5-input OR. The four inputs connect to the negated outputs of counter 1 (i.e. the \$\bar{Q}\$ outputs) and the fifth goes to the clock.
If you are wiring up the counters yourself, you can either do the same as in (1), or you can wire up the counter to be and 8-bit counter directly. If you look at your circuit, you should notice that there is a great deal of symmetry between each bit of the counter. Basically you add the same sub-circuit for each bit - so an 8-bit timer would just 8 of the sub-circuits chained together. An n-bit timer, is n of the sub-circuits.
Best Answer
Sorry, but not close. At a start, FF1, which I presume represents your lsb, should have its input tied to a logic high. I suspect that you intended FF3 to be the lsb, and that you have confused T flip-flops with D flip-flops. Try replacing your FFs with D-types.