32 x 8 Register file using generate statement for D-flip flops

vhdl

My circuit has a grid of 32 x 8 D flip flops. each row should be producing a 32 bit vectors that contain the Q values from the D-ff's – which are then sent to a 8×1 MUX. The following code is me trying to properly generate the 32 x 8 D flip flops and test if I can get a vector out of them (the 32 bit I0 vector).

the circuit I'm trying to write the implementation for can be seen in the figure posted in this question:
https://stackoverflow.com/questions/22418555/test-bench-of-a-32×8-register-file-vhdl?rq=1

library ieee;
use ieee.std_logic_1164.all;

entity REG is
port (
    CLK         : in std_logic;
    WRT_REG_NUM : in std_logic_vector(2 downto 0);
    WRT_DATA    : in std_logic_vector(31 downto 0);
    READ_REG_A  : in std_logic_vector(2 downto 0);
    READ_REG_B  : in std_logic_vector(2 downto 0);
    PORT_A      : out std_logic_vector(31 downto 0);
    PORT_B      : out std_logic_vector(31 downto 0)
);
end REG;

architecture BEHV_32x8_REG of REG is
-- decoder component
component DCDR
    port (
        I_in    : in std_logic_vector(2 downto 0);
        O_out   : out std_logic_vector(7 downto 0)
    );
end component;
-- D flip flop component
component D_FF
    port (
        D_in    : in    std_logic;
        CLK     : in    std_logic;
        Q_out   : out   std_logic;
        QN_out  : out   std_logic   -- Q not
    );
end component;
-- MUX copmonent
component MUX
    port (
        S_in                            : in std_logic_vector(2 downto 0);
        I7, I6, I5, I4, I3, I2, I1, I0  : in std_logic_vector(31 downto 0);
        O_out                           : out std_logic_vector(31 downto 0)
    );
end component;

-- internal signals used
signal I_in     : std_logic_vector(2 downto 0);
signal O_out    : std_logic_vector(7 downto 0);
signal CLK_vals : std_logic_vector(7 downto 0);
signal I0       : std_logic_vector(31 downto 0);
signal QN_out   : std_logic_vector(31 downto 0);


begin

-- decoder instance
DCDR1 : DCDR port map(I_in, O_out);

GEN_D_FF1:
for ROW in 0 to 7 generate
    GEN_D_FF2:
    for COL in 0 to 31 generate
        DFF_X : D_FF port map(WRT_DATA(COL), CLK_vals(ROW), I0(COL), QN_out(COL));
    end generate GEN_D_FF2;
end generate GEN_D_FF1; 

DCDR_AND : process
begin
    I_in <= WRT_REG_NUM;

    for I in 0 to 7 loop
        CLK_vals(I) <= O_out(I) and CLK;
    end loop;
    wait for 10 ns;
end process DCDR_AND;

end BEHV_32x8_REG;

EDIT: adding a screen shot of a simulation run
Simulation

When I simulate the above code in ModelSim, I don't get any output for I0. Where is my design flawed? Am I violating any VHDL best practices? Assuming I can get this to function properly, how could I get 8 different 32-bit vectors (from each row of flip flops) to send to the MUX(s)?

I appreciate any advice I receive!

Best Answer

Flip-flops trigger when the CLK value changes (assuming your flip-flop code is correct here). Your flip-flop component,

component D_FF
    port (
        D_in    : in    std_logic;
        CLK     : in    std_logic;
        Q_out   : out   std_logic;
        QN_out  : out   std_logic   -- Q not
    );
end component;

has the CLK input tied to CLK_vals(ROW), from this line:

DFF_X : D_FF port map(WRT_DATA(COL), CLK_vals(ROW), I0(COL), QN_out(COL));

Yet the CLK_vals never change, as evident by your timing diagram, after the initial 10ns wait when it is uninitialized.

Your CLK_vals is setup here:

CLK_vals(I) <= O_out(I) and CLK;

Yet neither O_out nor CLK change.

O_out stays '00100000', and CLK stays '1'

You need to have an alternating clock. Something simple, like 

signal CLK : std_logic := '0';
CLK <= not CLK after 5ns;

I have read both sides of the fence as far as needing to initialize values, you can read a little bit about that here. But it would get rid of those ugly red Us

https://stackoverflow.com/questions/6363130/is-there-a-reason-to-initialize-not-reset-signals-in-vhdl-and-verilog

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