Electronic – VHDL generate statement increment by 2

vhdl

I'm trying to use a generate statement to make a custom bit width version of my circuit. However, I need to increment N by 2 instead of 1. Is there a way to do this?

...
adders: for N in 1 to bits-1 generate
        mapping: RBNS port map(
            a => a(N downto N-1),
            b => b(N downto N-1),   
            sum => result(N downto N-1),
            cout => carry(N),
            cin => carry(N-1)
        );
        end generate;
carry(0) <= '1'
...

Best Answer

You can multiply the iterator :

adders: for N in 1 to bits/2-1 generate
        mapping: RBNS port map(
            a => a(N*2 downto N*2-1),
            b => b(N*2 downto N*2-1),   
            sum => result(N*2 downto N*2-1),
            cout => carry(N*2),
            cin => carry(N*2-1)
        );
        end generate;
carry(0) <= '1'

... etc

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