BASYS2 – Verilog: how to properly edit ucf file

fpgaspartan-3verilogxilinx

I am a newbie at FPGA. I bought BASYS2 digilent board(Spartan3E). I have background on microcontrollers. C/C++ is no problem for me. But I am having some
trouble with FPGA. Actually, not with FPGA but with Compiler and ISE. As
you can see in the screenshot below, I configured the FPGA chip.

This is the implementation code:

module myModule(A, B);
    input wire A;
    output wire B;
    assign B = !A;

endmodule

And this is the ucf code:

# Onboard LEDs
NET "B" LOC = "M11";

NET "A" LOC = "C11";

As boards technical sheet says, M11 is LED 1 and C11 is BTN 2. So I want
LED to flash when I unpress the button. Do you see something wrong with
the code? Because it aint working. If the code should have been working,
what should I do? Am I skipping something?

As you see I aldready generated programming file and run. So what next?

Thanks.

Best Answer

Go to project->Design Properties and under Project Settings make sure that everything is configured correctly for the BASYS2. Make sure you have the correct family and device selected.

I've attached an image which I believe has the correct settings for your board. Check to make sure yours match!

Related Solutions

Electronic – Hello world VHDL program – blinking LED

Have you simulated the code to make sure it does behave OK in the ideal world?

Also, 100MHz is quite a fast clock and unless you tell the tools that's how fast you want to go, you might find it doesn't work. The logfiles should report what the final timing numbers are. You don't need to use a DCM, but if you want to, in the libraries guide there is a sample VHDL instantiation template, or you can use CoreGen.

As others have said, it's conventional to use the rst signal to reset your design, especially your counter. With FPGAs you can get them to startup in a known state. but it's often easier (especially to get it to match with simulation) to have an explicit reset. When you do this, check the polarity of the reset signal - sometimes they are active-high and sometimes active-low.

If you are using XST for synthesis, it should work fine with initial values. And even if it doesn't, the blink inversion will work, it'll just start from '0' not '1'. And the counter will start from all-zeros.

So:

Simulate the design, make sure it toggles in simulation first.
Add a PERIOD constraint to the UCF file to put a 10ns constraint on the clk signal.
Also, check the .pad file to see that the things you think you have constrained to the pins actually have gone on the right pins.

Problem compiling verilog

One possible cause: Synthesis is merging vga_g, vga_b, and vga_r into a single net, because they are all equivalent. Then the translate step can't put them in different locations, because there's only one net in the synthesis output.

Solution 1. Explicitly instantiate your OBUFs.

 OBUF obuf_vga_g ( .I ( on ), .O ( vga_g ) ); 
 OBUF obuf_vga_b ( .I ( on ), .O ( vga_b ) ); 
 OBUF obuf_vga_r ( .I ( on ), .O ( vga_r ) );

This makes it explicit in your code that the output nets are buffered from the on signal and attached to output pins. Obviously the tool should already know these nets are connected to output pins because they're outputs of the top level module. Having to do this kind of thing is just one of the quirks of using a tool originally designed to describe logic for the different purpose of designing logic.

Solution 2. Use constraints to eliminate merging of duplicate logic.

Depending on which synthesis tool you use, there should be a constraint available that you can attach to your vga_b, etc, signals to prevent them being merged in the synthesis step. In Synplicity, I believe you would use syn_keep to prevent removing redundant combinatorial logic.

As Apalopohapa noted in a comment, you might also need to turn on a flag to enable Synthesis to automatically generate the OBUFs you need. This should default to 'on', but it doesn't hurt to double-check it.

Best Answer

Related Solutions

Electronic – Hello world VHDL program – blinking LED

Problem compiling verilog

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