Electrical – How to create .VCD file or Simulation activity file of verilog code

verilogxilinx

I have Verilog's code. It is simulated correctly and synthesize too. I wanted to write.VCD(value change dumped) file.
I got from internet few command to generate VCD file as given below: 

initial begin
$dumpfile ("invchn26.vcd"); // Change filename as appropriate. 
$dumpvars(1, t.uut); 
end

But have few amount of confusion:
1. The above lines will be written on the testbench. Am I right?
2. I have below files:
testbench: stimulus.v ,
the main file named F_E. it is instance by name call in stimulus file. like written as F_E call (a,b,CLK,x,y);
I wrote below lines in stimulus (testbench file) : 

 initial begin
    $dumpfile ("crt.vcd"); // Change filename as appropriate. 
    $dumpvars(1, stimulus.call); 
    end

But its giving error.
How DO I create .VCD file with verilog and xilinx.
Please suggest hints.

Best Answer

(I show an example on linux, the steps with new names to avoid mixing the names and modules with your filenames.)

If you have a file, let´s say, "counter.v", then you would write a testbench file, say "counter_tb.v" (for the sake of clarity, it is better to name the testbench file "something_tb.v" for the file "something.v"). In the testbench-file, you give the vcd file name, as you mentioned:

$dumpfile("counter.vcd")
$dumpvars(0, counter_tb)   <= Name of the testbench module

In the testbench file, there has also to be the include command for the module under test: 

`include "counter.v"
 module
     counter_tb();
 ...
 ...

Then you would compile (on Linux): 

iverilog -o counter counter_tb.v

Then this can be processed with the command

vvp counter

which produces the output-file "counter.vcd" which can be inspected by the command 

gtkwave counter.vcd

If all the steps above where correct, there should be no complain

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