Electrical – Verilog Register File

registersystem-verilogverilog

I wrote a verilog code for a 4 by 9 bit register:

module reg_file(input rst,
            input clk,
            input wr_en,
            input rd_en,
            input [1:0]rd0_addr,
            input [1:0]rd1_addr,
            input [1:0]wr_addr,
            input [8:0]wr_data,
            output reg [8:0]rd0_data,
            output reg [8:0]rd1_data);

    reg [8:0]mem[3:0];
    integer i;

    always @(posedge rst or negedge clk)
    begin
        if (rst) begin
            for (i=0; i<4; i=i+1)
                mem[i]=0;
        end
        else if (wr_en) begin
            mem[wr_addr]=wr_data;
        end
        else (rd_en) begin
            assign rd0_data = mem[rd0_addr];
            assign rd1_data = mem[rd1_addr];
        end
    end
endmodule

but using iverilog to check if there are any issues, it says:

26: syntax error
27: Syntax in assignment statement l-value.
30: syntax error

I can't seem to figure out why I'm getting these errors, can anyone help?

I also need to find test vectors to test every possible outcome of the register file, does anyone have any suggestions on the best way to do that?

Best Answer

Those numbers at the front of the error messages are line numbers. Open your verilog file in a text editor that displays line numbers, and figure out where they are.

One problem I noticed was on the line:

else (rd_en) begin

You can't have a condition after else without another if keyword.

else if (rd_en) begin

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The most likely cause though as far as I can tell from what you have posted comes down to the way you are simulating the code. It would be good if you posted the code you used for simulation.

It is entirely possible that if you are using something like blocking statements to generate both the oe signal and clk signals in a testbench setup that the simulator gets confused and deasserts oe a very short amount of time before the rising edge of the clock which you wouldn't necessarily be able to see on a waveform view (it would look like it was changed on the clock edge), but would (in an RTL simulation at least) result in the behaviour you are seeing.

In practice it wouldn't happen as all the logic including the oe signal would be synchronous.

I'm going to post this bit as part of my answer rather than a comment as it allows better code formatting, but consider this alternative arrangement:

always @(posedge clk) begin
    if (reset) begin
        oe_hold <= 1'b0;
    end else begin
         if (oe && (oe_hold | we)) begin 
             oe_hold <= 1'b1;
         end else begin
             oe_hold <= 1'b0;
         end
    end
end

Notice how now rather than trying to set oe_hold to \$0\$, then at the same time (non-blocking!) trying to set it to a \$1\$ if the conditional was true. Now it specifically sets it to \$0\$ only if it wasn't true. The if/else is of course equivalent to simply: oe_hold <= (oe && (oe_hold | we));.

This may or may not help with the issue depending on how your simulation software handles the conflicting assignment of your code. In practice it seems to synthesize to the same thing (in Quartus II at least), but I have seen odd behaviour from some simulators getting confused with certain constructs.

_{Note: I added some extra begin/end statements, though that was only to improve readability.}

I also want to pick up on something in your question, you mentioned driving one signal on one clock edge and another on the opposite clock edge. In synchronous logic you should try to avoid this as it can lead to timing issues in the design - you basically make all your setup requirements twice as stringent (because the effective clock frequency is doubled!). Everything in a synchronous circuit should be clocked on the same edge.

Port full register file from/to a verilog modue

With Verilog you cannot have an input or output port with more than one dimension - so you can't declare a 2D array to be an input or output.

Instead you need to pack the array into a single dimension which can be done using a generate loop.

Best Answer

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Port full register file from/to a verilog modue

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