I am designing a shift register. It has a control signal called RD which is asynchronous (so cant use it inside the procedural block), the whole point is my n-1 bit shift register is value of the input if RD ==1 or else it has high impedance; I am not sure how to write the assign the high impedance value because my n bit is a parameter so I cant define the no of bits.
inout [n-1:0] Data;
input RD;
reg [n-1:0] register; //my register
Example: Data = (RD==1'b1)? [n-1:0] register: 'z ;
its giving me a error. How can I define that if RD is 1 then I need to see what is there inside the register and if its 0 then, it should be high impedance. Can anyone help?
Best Answer
Unless you are using SystemVerilog, you cant declare a constant like that.
Instead use the replication operator.
{(WIDTH){1'bz}}
is aWIDTH
bit wise constant of allz
's. Just replace the width with however wide you need (can be a parameter).Furthermore, it should be
register[n-1:0]
not[n-1:0]register
.The following should work: