How to define port in test bench

system-verilogverilog

module stimulus;
  wire [3:0] max,med,min;
  reg [3:0] a,b,c;
  reg cin;
  sorting_three three(max,med,min,a,b,c,cin);

  initial begin
    a=4'b0010;
    b=4'b1001;
    c=4'b1010;
    cin=1'b0;
  end
endmodule

The above code giving correct result after Simulation. When I try to view RTL schematic. Its is giving error like:

ERROR:Xst - "stimulus.v" line 22: Module  has no port.
-->

Total memory usage is 123976 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)


Process "Synthesis" failed

How to define port of stimulus( it is test bench)? I think wire and reg is sufficient to define input and output port. If it is not then what correction required to get correct RTL schematic.

Best Answer

All modules need a list of ports, for example

module mymodule(port_a, port_b);

For a test bench module this list is empty, but it still needs to be there:

module stimulus();

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System verilog: define empty vector

You want to use the let statement instead of a union. The let statement is like a macro, except it is limited to a scope, and limited by substituting expressions, not any arbitrary text.

module example #(int ITEMS=3)(output logic[4:0] result);
  let systemstatus = result[4];
  let itemStatus = result[ITEMS-1:0];
  ...
endmodule

If you still want do this using a union, you can get what you want by creating your union with two structs. Also note that you need to use a packed union and struct to guarantee bit alignment.

union packed {
  logic [4:0] result;
  struct packed {
    logic status;
    logic [3:0] padding;
  } system;
  struct packed {
    logic [4: 1+4-ITEMS] padding;
    logic [ITEMS-1:0] status;
  } item;
} myStruct;

Now you can refer to mystruct.system.status and mystruct.item.status.

Electronic – Verilog test bench incorrectly reading test vector

The clue is in the warning messages at the beginning of the simulation:

WARNING: testbench3.v:17: $readmemb: Standard inconsistency, following 1364-200 .
WARNING: testbench3.v:17: $readmemb(xor_4.tv): Not enough words in the file for the requested range [0:10000].

Each entry of testvector is 4 bits wide, however xor_4.tv is 5 bits and {a,b,c,d,yexpected} is also 5 bits.

Change reg [3:0] testvector [10000:0]; to reg [4:0] testvector [0:10000];

Best Answer

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System verilog: define empty vector

Electronic – Verilog test bench incorrectly reading test vector

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