Task in verilog code

verilog

I am using task in my module in verilog coding, and facing problem, in passing the argument values. actually The variables defined in the task block as input are not receiving the values that are passed to them while calling this task.
Here is the code

module carry_addr(Cin,A,B,Sum, Cout,rst_n );
parameter width=3;
parameter bits=1;
input [width:0] A,B;
input Cin,rst_n;
output reg [width:0] Sum;
output reg Cout;
integer k;

reg [width+1:0]C2;

task fulladder;
input A1;
input B1;
input C4;
output reg Sum1;
output reg C0;
begin

        Sum1=0;
        C0=0;
      {C0,Sum1}=A1+B1+C4;
end 
endtask


task automatic ripple;
input [bits:0] A2;
input [bits:0] B2;
input C1;
output reg [bits:0]sum2;
output reg cout;
reg [bits:0]sum3,sum4;

reg [bits+1:0] C,C3;
begin

            sum2=0;
            sum3=0;
            sum4=0;
           cout=0;
            C=0;
            C3=0;

            C[0]=0;        
            C3[0]=1;
            for (k=0;k<=bits;k=k+1)
            begin 
                 fulladder(A2[k],B2[k],C[k],sum3[k],C[k+1]);
                 fulladder(A2[k],B2[k],C3[k],sum4[k],C3[k+1]);

            end
            if(C1==0)
            begin
                cout=C[bits+1];
                sum2=sum3;
            end
            else if(C1==1)
            begin
                cout=C3[bits+1];
                sum2=sum4;
            end

end
endtask


always@(rst_n or A or B or Cin)
begin
    if(!rst_n)
     begin
            Sum=0;
            Cout=0;
            C2=0;
     end


         C2[0]=Cin;
         for (k=0;k<=width;k=k+bits+1)
         begin
              ripple(A[k+:bits],B[k+:bits],C2[k],Sum[k+:bits],C2[k+bits+1]);

         end
         Cout=C2[width+1];


end


endmodule

in this specifically, A,B 's values are not copying in the A2,B2 variables in the ripple task.

Best Answer

The issue could be stemming from the fact that you don't have any delays in the verilog code under the for loop (including the code included in the tasks). There could be multiple driver issue.

You can try adding #1 in your for loop and see if that helps.

I notice that the question is pretty old. Might be useful for future exchangers.

Related Solutions

Clock Period using Verilog code

Verilog offers three system tasks related to the simulation timestep:

$time returns the current time as a 64-bit integer, in units of the timestep defined by the `timescale directive.

$stime returns the same value as a 32-bit integer.

$realtime returns the same value as a real number.

However none of these system directives are likely to be useful for synthesis. They would normally be implemented by special code in the simulator that accesses variables in the simulator program.

To keep track of time in a real circuit, you need to start with an input clock with a known frequency. For good accuracy you'd generate this with a crystal oscillator circuit, which would be entirely outside your device if you're working on an FPGA.

Then you simply build a counter to keep track of ticks of your clock (note code not tested):

module time_counter(input clk, input rst, output reg [31:0] ticks) 

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            ticks <= 32'h00000000;
        end 
        else begin
            ticks <= ticks + 1;
        end
    end
endmodule

There is a limit to how fast a counter like this can operate, and various tricks to build faster counters if needed.

If you need to find the period of an input with an unknown period, you need to compare it to a clock with a known period. It's simplest conceptually to make the known clock much faster than the unknown clock and count ticks of the known clock for each period of the unknown clock. If that's not possible, you can divide the unknown clock by some factor (say 16 or 128 or 1024) and count ticks of the known clock for each cycle of the divider to work out the unknown period.

Test_bench in Verilog using Task

It would be helpful if you could clarify this statement :

How should I define input in argument in task so that input should be given independently?

A task defined as:

task display_redux
  input [31:0] a_number;
  begin
    $display("display_redux was sent : %d", a_number);
  end
endtask

Can be called with :

display_redux(20);
integer ii = 6;
display_redux(ii);

To me the input here is independent from anything else, and you can not assign value to the input so it does not have side effects from of modifying inputs from where it was called.

Taking one of your tasks:

task exp_case_2b
  input data_i;
  input reset;
  input read;
  input dcsel;
  input xlat;     
  output reg [47:0] data_o;
  begin
    repeat(47)begin @(posedge clk)
      data_i = 1;
      reset  = 0;
      read   = 0;
      dcsel  = 0;
      xlat   = 1;
      data_o = Data_out;          
    end
    #5250 compare_data_2(data_out_tb);
  end 
endtask

Youve declared many inputs which you are not driving when you call it with exp_case_2b(data_out). You have defined inputs then are trying to drive values on to them. You need these to be regs and not inputs so they are local to the task. Or not defined at all and use hierarchical references to the top level reset, aka tb.reset = 0;.

I think this might have been what you were trying todo:

task exp_case_2b
  input      [47:0] data_i;     
  output reg [47:0] data_o;
  begin
    repeat(47)begin @(posedge clk)
      data_i = 1;
      reset  = 0;
      read   = 0;
      dcsel  = 0;
      xlat   = 1;
      data_o = Data_out;          
    end
    #5250 compare_data_2(data_out_tb); //No idea where this variable comes from
  end 
endtask

Then call :

 exp_case_2a(data_i_t, data_out_1);

Best Answer

Related Solutions

Clock Period using Verilog code

Test_bench in Verilog using Task

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