Electrical – Verilog code for frequency divider

Rather than addressing the many problems in your source code, let me just show how I'd implement the module you describe.

First, I wouldn't use a sub-module to build the adder; synthesis tools are perfectly able to create adders from behavioral code. Secondly, an elaborate state machine isn't required; the module can simply produce a final result four clocks after each activation of the start signal. I've added a done signal to the module interface to make this explicit.

module seq_mult_4bit (
  output  [7:0] product,
  output        done,
  input   [3:0] a,
  input   [3:0] b,
  input         clock,
  input         start
);

  reg     [7:0] product;
  reg     [3:0] multiplicand;
  reg     [3:0] delay;

  wire    [4:0] sum = {1'b0, product[7:4]} + {1'b0, multiplicand};

  assign done = delay[0];

  always @(posedge clock) begin
    if (start) begin
      delay = 4'b1000;
      multiplicand = a;
      if (b[0]) begin
        product <= {1'b0, a, b[3:1]};
      end else begin
        product <= {1'b0, 4'b0, b[3:1]};
      end
    end else begin
      delay = {1'b0, delay[3:1]};
      if (product[0]) begin
        product <= {sum, product[3:1]};
      end else begin
        product <= {1'b0, product[7:1]};
      end
    end
  end

endmodule

If you really want to use an external module for the adder (which is really the point of your question), simply substitute the wire declaration above with the following block of code:

  wire   [4:0] sum;

  rca_4bit adder (
    .sum        (sum[3:0]),
    .c_out      (sum[4]),
    .a          (multiplicand),
    .b          (product[7:4]),
    .c_in       (0)
  );

Let me know if you have any specific questions about how this implementation works.

Your first problem is here:

module d(q,q1,d,c); //D Flip Flop
output q,q1;
input c,d;           // Line A
// ...
    always @ (posedge c)
       begin 
         q=d;
         q1= ~d;
         d=~d;       // Line B
        end
endmodule

If you make d an input to a module (in line A), you should not be driving it like you are in line B. The inputs to d should be driven by something in the upper-level module that instantiates d.

(You also assign an input of the d module when you instantiate a clock within it and connect the clock's output to an input signal.)

Your second problem is that you defined three modules, but you never instantiated them anywhere. You need to make a "main" or "top_level" module that instantiates at least one instance of each of your sub-modules, and tells how they're connected to each other.

In this setup having instantiated a clock module each in the D and JK Flip Flop module can I expect the clock (output signal generated by module clock) in sync in both these modules or should I expect a lag equal to the delay of actual instantiation of the clocks when the simulation started?

They will be in sync, but only because the simulator is idealized. All initialization happens effectively at the same time. However, your clock module is not synthesizable code, because it relies on a magical "#200" delay without any indication how that would be produced in a physical circuit.

So, in simulation, your two modules (if you actually instantiated them somewhere) would operate in sync. But the usual way to do things is to make a main module, instantiate one clock module there, and use its output as the c input for instances of the two flip-flop modules. (If you actually made clock to be a synthesizable design, this would also save resources by not creating two copies of it when you only need one)