Electrical – Checking array input value Verilog

verilog

How can I check the value of array input in Verilog? I tried this code but, I got an error "op_code is not a constant"

module mutlti_proccessor(data_out, flags, data_1, data_2, op_code);
    input [7:0]data_1;
    input [7:0]data_2;      
    input [3:0]op_code;

    output [7:0]data_out;
    output [4:0]flags;
    /* flags[0]:ZF "Zero Flag", flags[1]:SF "Sign Flag", flags[2]:CF "Carry Flag", 
       flags[3]:OF "Overflow Flag", flags[4]:COF "Compare Flag" */

    wire carry;

    /* Set falgs to zero */
    assign {flags[0], flags[1], flags[2], flags[3], flags[4]} = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };

    if(op_code==00000)
        Ripple_Adder RA1(data_out, carry, data_1, data_2, 0);


endmodule

Where Ripple_ADD is another module that sums up two 8-bit numbers.
Note: there is no clock.

Thanks ….

Best Answer

Your problem lies in the line of code:

if(op_code==00000)
     Ripple_Adder RA1(data_out, carry, data_1, data_2, 0);

You don't seem to have understood that Verilog is a "Hardware Description Language", not a procedural programming language. It does not execute code line by line, but rather is synthesized into hardware based on what you are describing.

You are trying to use an if statement incorrectly. What your code is describing is that if the op_code is 0, then create some hardware called Ripple_Adder. However, what happens if op_code is not 0? Does it need to infer the adder? Should it delete the adder?

Simple answer, it can't - the hardware is fixed at synthesis, you can't add or remove bits of it when running. This is why it is complaining about op_code not being a constant - it doesn't know whether or not Ripple_Adder should be included or not.

The solution, is to always include the hardware, and then infer a multiplexer to select whether or not the output of it is used. Something like this:

wire [7:0] ripple_data_out; //Output data for the ripple adder
Ripple_Adder RA1(ripple_data_out, carry, data_1, data_2, 0); //Infer the ripple adder

always @ * begin
    case (op_code)
        5'b00000: data_out = ripple_data_out; //If the op_code matches, connect ripple_data_out to data_out through the mux.
        //... Add more cases here for other op_code values ...
        default: data_out = 8'b0;
    endcase
end

Related Solutions

Electrical – Synthesizeable D Flip flop for FPGA

Your flip-flop implementation is correct.

What @duskwuff is pointing out is that when you implemented your test waveform (c and d) you have d transitioning at the exact same time as c. This is not how whatever is driving your flip-flop will really work. The input has to be set up before the clock edge. If the input is transitioning at the clock edge--remember that while the edges look square in the logic analyzer, in reality the voltage takes a certain amount of time to transition from one state to another--your flip-flop may read high, low, or some intermediate voltage that may really confuse your logic.

You can see what I'm talking about in your screen shot.

At the first positive clock edge, d transitions from low to high. But because the new value of d (high) was not set up before the clock edge, your flip-flop sees the original value (low) and outputs that on q. The same thing happens on the second positive clock edge.

However, between the second and third positive clock edges, at 140ns, you change d from low to high. So when the clock goes positive the third time at 150ns, it sees the high value, and then q goes high about 8ns later.

Your test sequence should look something like:

set clock high
wait 1/4 clock cycle
set d to some value
wait 1/4 clock cycle
set clock low
wait 1/2 clock cycle
set clock high (it's now been one full cycle from last positive edge)
wait 1/4 clock cycle
check q

Electrical – Erratic behaviour in FPGA based I2s loopback (Verilog + Spartan6)

This looks a lot like issues associated with not synchronizing all of your inputs into the main clock domain. You should always be running all of the input signals through flip-flops before you use them for anything.

As for your 12.288 MHz clock out; use an ODDR2 element to drive it like so:

ODDR2 #(
    .DDR_ALIGNMENT("C0"),
    .SRTYPE("ASYNC")
)
oddr_inst (
    .Q(clk_out),
    .C0(clk),
    .C1(~clk),
    .CE(1'b1),
    .D0(1'b0),
    .D1(1'b1),
    .R(1'b0),
    .S(1'b0)
);

Note that the global clock pins are only required to bring clocks IN to the FPGA. Driving clocks out can be done on any pin, and the recommended way to do so is with a DDR flip flop so that you can precisely generate an inverted clock that exactly aligns with data from IOB flip flops driven by the same clock.

Best Answer

Related Solutions

Electrical – Synthesizeable D Flip flop for FPGA

Electrical – Erratic behaviour in FPGA based I2s loopback (Verilog + Spartan6)

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