Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite.
Starting with a simple D flip flop, I face the first road block.
Problem Statement: The output(Q) of a D-FF is required follow the input signal (as it should be), and here goes the code:
//----------------------------------------
//module D flip flip
//-----------------------------------------
module d(q_w,q0_w,d,c);
output q_w,q0_w;
input c,d;
//wire c;
reg q,q0;
wire q_w,q0_w;
assign q_w=q;
assign q0_w=q0;
initial
begin
q=1'b0; q0=1'b1;
end
always @ (posedge c)
begin
q<=d;
q0<= ~d;
end
endmodule
The input signal 'd' also transitions at the same positive edge of a common clock signal ('c' for module D-FF). This is causing the circuit to not behave properly as the transition and testing happens at same edge of clock. Also that I have read it is better to stick to one edge of clock in designs (as a good practice) and am hence abstained from using negative edge of the clock.
Having encountered the same issue when simulating I used a delay to do away with the problem
always @ (posedge c)
begin
#2 q=d;
q0= ~d;
end
Despite searching a lot I cant figure out a way to implement the functionality as required in the hardware. I tried adding buffer elements before the clock signal enters D-FF module but in vain.
PS: I haven't yet burnt any of this on the FPGA yet. My apprehensions are marked by the results of Quartus Simulation.
I have manually tweaked the input D at point to check the follow up of the circuit
Best Answer
Your flip-flop implementation is correct.
What @duskwuff is pointing out is that when you implemented your test waveform (c and d) you have d transitioning at the exact same time as c. This is not how whatever is driving your flip-flop will really work. The input has to be set up before the clock edge. If the input is transitioning at the clock edge--remember that while the edges look square in the logic analyzer, in reality the voltage takes a certain amount of time to transition from one state to another--your flip-flop may read high, low, or some intermediate voltage that may really confuse your logic.
You can see what I'm talking about in your screen shot.
At the first positive clock edge, d transitions from low to high. But because the new value of d (high) was not set up before the clock edge, your flip-flop sees the original value (low) and outputs that on q. The same thing happens on the second positive clock edge.
However, between the second and third positive clock edges, at 140ns, you change d from low to high. So when the clock goes positive the third time at 150ns, it sees the high value, and then q goes high about 8ns later.
Your test sequence should look something like: