is it in general possible to implement a frequency doubler completely on FPGA? I saw some implementations on google by delaying the input and XORing it with the original. But they also say that this method is not reliable, and we may not achieve a 50% duty cycle output. I do not want to compromise on duty cycle because i may need to use the doubler 3 times to achieve a x8 frequency
The input clock undergoes a +/- 5% jump in frequency (from 13.56 Mhz) every 30 us.
I tried using a DCM – while the input to the DCM jumps at an instant, the output from the DCM gradually drifts to the required frequency over a span of 20 us. This timing is unacceptable because we jump in frequency every 30 us and we cannot have drifting clock for 20 us of 30 us.
The input clock comes from an external DSP processor, using two DDS (Direct Digital Synthesis) blocks to generate the 13.56 Mhz signal on two ports. The DDS jumps the frequency of the 13.56Mhz every 30 us and also varies its phase from -45deg to +45deg, whilst the other varies phase in the opposite direction. These two 13.56 Mhz signals are enter the FPGA domain.
The FPGA produces 8x signals from these two inputs, totally 16 in number and varying in steps of 45 degrees wrt each other. Currently the FPGA uses a DCM and flip flops to do this. The 13.56 Mhz is fed to the DCM and 8x clock comes out of it. Both the input to the DCM and the output from the DCM are fed to a phase shifter module which shifts the input clock by the period of the 8x clock (45 degrees). All this works fine without frequency jumping but fails due to frequency jumps.
Best Answer
All of the DCM blocks (digital clock managers) in FPGAs I've worked with can scale up and shift clock frequencies cleanly. Ensure that your input base clock arrives on a specific clock pin if you can, as this will introduce the least skew routing to the dcm.
If you want more specific guidance, which part are you targeting and what frequencies? If you are targeting Ghz for instance on a cheap part, it probably isn't going to happen.
The DCM blocks often have multiple outputs that can be driven to different frequencies from the same base clock, so all your generated clocks can have a common duty and phase.
Edit: I see the sorry history of your previous questions clocking on spartan6 FPGAs and Spartan 6 DCM unstable clock output - Please link the questions in future.
As other commenters have noted, what you are asking is impossible in the general case. A clock management unit cannot be both stable (rejecting noise on the base clock) and respond to linear/step changes in the input quickly. These are contradictory design goals.
If I were you, I'd settle for a nice stable, fixed clock coming into the FPGA, and then re-program the DCM module's output clock ratios using logic in your design. I know offhand that the StratixV parts have a bus into the DCMs to allow ratio and phase changes while operating. This should avoid the need to settle and lock the input clock each time.
Whatever feedback or user interface you use to make these adjustments would then be done by the FPGA, e.g. decoding UART instructions from a PC or scanning keypad/switches.
Have a look at this Xilinx App Note, it suggests the Spartan 6 PLLs do have a dynamic reconfiguration port for doing this sort of thing: http://www.xilinx.com/support/documentation/application_notes/xapp879.pdf
Update: If for some reason you really need to have the input coming from a varying clock, you may choose to design an input stage that measures the frequency of the input clock against some stable base clock, measuring the frequency shift (in Hertz) and uses this to dynamically reprogram the DCM. This is advanced stuff, theres probably only a few dozen engineers in the world who use the dynamic ports on FPGAs. It may need some analogue design, eg. an external beat-mixer/Heterodyne first to get enough resolution on . Expect to have to raise a few queries with Xilinx to get it all working.