Assume we have a simple Verilog module with 1 input (in1) and one output (out). Please look at the truth table at the end of this question.
I want to send a signal with the voltage between 0-VCC0=3.3v to input in1=PIN3 of a FPGA ( this case XC3S400). All Vref pins of the relative bank are connected to 1.8V. Now I want to see a logic 1 on out=PIN4 when the voltage of in1 is higher than verf and a logic 0 when it is less.
I know it is a feature of single ended I/O standards that is supported in FPGAs but I don't know how to assign this vref comparison in ISE. I just can guess to write some attributes in the verilog or assigning vref in ISE (PlanAhead).
In ISE Plan Ahead , one can assign fixed vref standards ( GTL, GTLP,…). but these are fixed Vref standards. I am looking for a way to set vref to any voltage which is desired. For example can I set vref to GTL=0.8v but connect 1.8v to vref pins of the bank?
Best Answer
You don't do it in the Verilog code.
If you assign a Vref-using IOSTANDARD to the pin in question in the UCF file (either by writing the text, or using Planahead to create the constraints), then the FPGA will use the Vref pin.
The "Spartan-3 Generation FPGA User Guide", Table 10-16 shows the IOSTANDARDs you can choose from to make use of Vref - in summary, it is HSTL, SSTL, GTL and their variants.
Edit: You might be able to achieve an arbitrary Vref for inputs by using an HSTL/SSTL/GTL input and the Vref as you have it (even though that's not the "right" vref for the standard). I've never tried it.
Alternatively, can you use a differential input instead and connect your reference 1.8V to the _N pin of the differential pair? That involves the PCB being laid out differently, so it might be too late!