Electronic – use differential I/O pins of FPGA as high speed comparator

Now fixed. The LMH7322 has ECL outputs. It is capable of providing LVDS levels, but this is not true LVDS. The outputs therefore need termination to ground (or another voltage below VCCO-2V).

I replaced the single 100 ohm termination resistor between the outputs with two 50 ohms, each to ground, and now the output is as expected. There are therefore a couple of problems with the model in the simulator: the device works fine with VCCI at +3.4V (as in first figure) and the model does not model the outputs as ECL.

Thanks to all for your comments.

You don't do it in the Verilog code.

If you assign a Vref-using IOSTANDARD to the pin in question in the UCF file (either by writing the text, or using Planahead to create the constraints), then the FPGA will use the Vref pin.

The "Spartan-3 Generation FPGA User Guide", Table 10-16 shows the IOSTANDARDs you can choose from to make use of Vref - in summary, it is HSTL, SSTL, GTL and their variants.

Edit: You might be able to achieve an arbitrary Vref for inputs by using an HSTL/SSTL/GTL input and the Vref as you have it (even though that's not the "right" vref for the standard). I've never tried it.

Alternatively, can you use a differential input instead and connect your reference 1.8V to the _N pin of the differential pair? That involves the PCB being laid out differently, so it might be too late!