Electronic – How to use different 7-segment for different numbers in FPGA board

fpgaverilog

I'm working working with NEXYS4DDR board which has two 4-digit 7 segment displays. Using the proper binary-bcd converter I can display numbers, the problem is… the same number is displayed in all the displays (assuming all are activated), like: 1 1 1 1 1 1 1 1 because I can only control one set of segments (CA, CB, CD, CE, CF, CG) and not one set of segments for each display. How can I separate them? To show, like 1 2 3 4? A SystemVerilog or Verilog solution would be preferred since that's the HDL I'm currently learning.

For reference, the board is: https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start

Best Answer

You need to sequence through the digits, one at a time, and light the appropriate segments for that particular digit. So you need one 7-segment decoder only and a multiplexer to select the appropriate 4 bits for that digit. Plus a clock and decoder for the digit select and a 3-bit 0..7 counter for 8 digits.

1kHz is more than fast enough for visual fusion to take place so the display does not appear to flicker, so you might use a 5 or 10kHz clock.

It's good practice to insert a bit of dead time to allow the current to tail off in the drivers so you don't get ghosting (part of one digit shows up in the next). A microsecond or so should suffice.