Electronic – Multiple LED outputs on FPGA using Verilog

fpgaledverilog

I made a simple 0 to 9 up counter using Verilog. The output is 4 LEDs which are turned on when their corresponding bit is 1. The code synthesizes fine, but on the FPGA, only one LED lights on and off repeatedly. The other three LEDs do not light up at all.
Here is my code:

module counter(
   input wire clock,
   input wire reset,

   output wire [3:0] o_number
);

reg [3:0] cur_state;
reg [3:0] next_state;

always @(posedge clock or posedge reset) begin
   if (reset) cur_state <= 4'b0;
   else 
    cur_state <= next_state;
end

// Next state function
always @(*) begin
   if (cur_state == 4'b1001) next_state = 4'b0000;
   else next_state = cur_state + 4'b0001;
end

 // Output function
assign o_number = cur_state;

endmodule

module display(
   input wire [3:0] inumber,

   output wire [3:0] LEDs
);

assign LEDs = inumber;

endmodule

None of the LEDs are broken as they all light up when tested individually. Clock has been adjusted so its period is around 2 seconds.

Please help me out. Thank you.

I revised the counter module. Here are all the files I used:

top.v

module top ( input wire clock, input wire reset, output wire [3:0] LEDs);
counter c1 (.clock(clock), .reset(reset), .o_number(number));
display d1 (.inumber(number), .LEDs(LEDs));
endmodule

counter.v

module counter ( input wire clock, input wire reset, output wire [3:0] o_number);
reg [3:0] cur_state;
always @ (posedge clock or posedge reset) begin
    if (reset) cur_state[3:0] <= 4'b0000;
    else begin
        if (cur_state[3:0]==4'b1001) cur_state[3:0] <= 4'b0000;
        else cur_state[3:0] <= cur_state[3:0] + 4'b0001;
    end
end
assign o_number[3:0]=cur_state[3:0];
endmodule

display.v

module display( input wire[3:0] inumber, output wire [3:0] LEDs);
assign LEDs[3:0] = inumber[3:0];
endmodule

top.ucf

NET "LEDs[0]" LOC = K12;
NET "LEDs[1]" LOC = P14;
NET "LEDs[2]" LOC = L12;
NET "LEDs[3]" LOC = N14;

NET "clock" LOC = T9;
NET "reset" LOC = L14;

Best Answer

There was a problem with the top module. I did not declare the wire that is used to connect the display and counter module.

Here is the revised top.v:

module top ( input wire clock, input wire reset, output wire [3:0] LEDs);
wire [3:0] number;
counter c1 (.clock(clock), .reset(reset), .o_number(number));
display d1 (.inumber(number), .LEDs(LEDs));
endmodule

The LEDs light up correctly according to each state now.

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