Cadence, BSIM3V3, and the Body Effect

From the graphs we see that gate leakage currents of all transistors decrease with increasing \$T_{OX}\$. This means that the increase in total leakage current must be attributed to subthreshold conduction.

Why would subthreshold current increase? The following equation for subthreshold curent appears in BSIMv4.7 User's Manual:

While there are many parameters involved, the main suspect is the treshold voltage, \$V_{th}\$, which is known to be sensitive to gate oxide thickness (as well as almost any other transistor's parameter).

In order to verify this I built the following circuit:

Sweeping \$T_{OX}\$ and measuring \$V_{th}\$ resulted in:

This linear decrease in threshold voltage explains an exponential increase in subthreshold leakage (based on the above equation).

The natural continuation of the answer would be to explain why \$V_{th}\$ decreases with \$T_{OX}\$. The equation used to calculate the threshold voltage for BSIMv4.7 model in Spice is:

\$T_{OX}\$ dependence appears in the above equation both explicitly (TOXE) and implicitly (through other parameters which depend on \$T_{OX}\$). It is beyond my expertise and knowledge to perform this task and map various numerical parameters into physical effects taking place in the actual transistor.

In summary:

The reduction in threshold voltage due to thicker oxide leads to higher subtreshold leakage current. The exact effects which cause the reduction are very complex.

The threshold voltage can be increased if the source is not connected to the body terminal. The threshold voltage is

$$V_T = V_{T0} + \gamma\sqrt{2\phi + V_{SB}} - \gamma\sqrt{2\phi}$$

where \$V_{T0}\$ is the threshold voltage when the source-to-body \$V_{SB} = 0\$, and \$\gamma\$ and \$\phi\$ are device parameters. If the NMOS source is connected to ground and so is the body then \$V_{SB} = 0\$ and \$V_T\$ is minimized (it's a similar argument for the PMOS).

So, yes, it is possible to adjust the threshold voltage by not connecting the NMOS body to the negative supply and the PMOS body to the positive supply.

However, this is usually not done intentionally. You typically want to minimize \$V_T\$ -- for example, this would allow you to use lower supply voltages.

The body effect is particularly undesirable for a common drain amplifier because it lowers the voltage gain. Without the body effect the unloaded voltage gain of a common drain amplifier is

$$\frac{v_o}{v_i} = \frac{g_m}{g_m + \frac{1}{r_o||r_{oc}}} \approx 1$$

where the approximation assumes the resistances are large. However, with the body effect the unloaded voltage gain is reduced:

$$\frac{v_o}{v_i} = \frac{g_m}{g_m + g_{mb} + \frac{1}{r_o||r_{oc}}} \approx \frac{g_m}{g_m + g_{mb}} < 1$$