Calculating Cpi with Miss Rate

You need to have some idea how long it takes the main memory to transfer a block of data corresponding to one "line" in the cache. The number you need to enter in this dialog is the number of CPU clock periods corresponding to that amount of time, for read operations and write operations, respectively.

For example, say your memory bus runs at 100 MHz and it takes three clocks to do a read (30 ns) and two clocks to do a write (20 ns). If your cache block size is 2 words, then the total time to read or write a block would be 60 ns and 40 ns, respectively. If your CPU is running at, say, 200 MHz (5 ns clock period), you would enter 12 and 8 into these fields.

If your main memory is more complex, such as DDR SDRAM that supports burst transfers and multiple banks, the calculation gets a little more intricate, but for the purposes of this simulation, an "average" figure for each kind of transfer should be adequate.

(I do not know any HDL, but I hope the following will be helpful anyway.)

One can use a 32-bit wide interface and implement atomic 64-bit loads/stores. For loads one can "cheat" by reading from the invalidated cache entry (only checking the tags on the first 32-bit load), since one knows that the two 32-bit accesses will be back-to-back and within the same cache block that is known to be a hit.

For stores, since the cache block must be in modified (or exclusive if silent updates are allowed) state to accept a store, an invalidate request (really read-for-ownership) generates a data response. Since a data response is provided and the total time of the write would typically only be two processor cycles, the data response could be delayed until the store has completed.

LDSTUB (load-and-store-unsigned-byte) and SWAP could be handled somewhat similarly to a 64-bit store by delaying the load until the cache block is in exclusive/modified state; the store part of the operation is known to be immediately after the read portion and a data response is required anyway, so the data response can be delayed slightly.

An alternative implementation of LDSTUB and SWAP could treat an invalidation between the load and the store as a miss for the load, effectively reissuing the load. However, this presents a danger of livelock. While livelock issues can be managed (e.g., various back-off techniques), the earlier mentioned implementation is probably much simpler.