Charge Cap Crystal – Package

Most likely the 22pF values used by TI are a compromise (cost / availability). The crystal can generally tolerate a few pF plus or minus the calculated value. I would guess that some empirical testing went into the decision to use 22pF instead of a closer value, or perhaps 22pF was already on the BOM.

Ultimately, even a calculation like what's in the datasheet is based on stray capacitance 'guesstimation'. You have to test whatever capacitor value you come up with and make sure that it works in your end product.

Also, page 20 of the C1111 datasheet that you linked to says 12-18pF is the range to use for the 32.768kHz crystal. Your mileage may vary.

The most important thing to keep in mind is that the capacitor should be tight tolerance with an appropriate dielectric material (one that isn't highly temperature dependent, such as NP0/C0G).

Further reading: here's a link to a good explanation of the topic of how crystals and capacitors interact.

At 16MHz matched length traces will not provide any benefit. They key however is to ensure that your GND return paths are short and that the crystal lines are isolated from clocking sensitive traces such as Uart RX or Reset lines, or any other functional traces to which coupled clocking could cause false interrupts or undesired functionality. To the Grounding, I would suggest placing some vias close to the GND paths of the load capacitors rather than relying on the GND trace back to the MCU. I generally place a 0.2/0.4mm via near every signal component ground pad where possible and at least 3 0.4/0.8mm vias for power or transient prone components. The general rule for noise/high speed is to keep your ground impedance as low as possible.

Your layout doesn't indicate whether the polygon pour on the bottom layer is ground, but in the event it is then I would suggest stitching it with some GND vias and applying a polygon GND fill on the top layer once your layout is complete. Try to stitch around any high speed or noise sensitive lines with GND vias.

Also, be mindful of trace-pad exits which are not at 90*. Acute angles between pads and traces will result in "acid traps" during the etching process and in the case of hand etched PCBs, may not etch correctly.

Also consider the local plane for VDD. Larger copper areas will be more susceptible to noise than wide traces with close grounding. I generally prefer to place such power fill on internal layers between GND planes for BGA escape. If your top layer is to be GND filled than this won't be a problem provided it is well decoupled.

Best of luck!