The two leftmost transistors forms a simple not gate, but it is powered only when \$V_{x1}\$ is high. Luckily enough the passgate on the right is turned on when \$V_{x1}\$ is low instead, and directly connects the \$V_{x2}\$ input to the output.
To sum it up:
- if \$V_{x1}\$ is high the output is NOT \$V_{x2}\$
- if \$V_{x1}\$ is low the output is \$V_{x2}\$
in a table:
x1 x2 out
0 0 0
0 1 1
1 0 1
1 1 0
that's a xor gate.
It's a normal effect.
in a), T1 is 'on', and you sweep the gate of T2. At say the midpoint of the sweep, T2 is partially on (say 5 V on the gate), and some current is flowing through it and T1. T1 being on doesn't mean it has zero resistance, and so T2's source is not at 0 V. Therefore its gate-source voltage is not the same as Uin.
conversely, in b), T2 is 'on', and you sweep T1. Now, the Uin value is equal to T1's gate-source voltage, and so, for a given Uin value, T1 in configuration b will be more 'on' than T2 would be in configuration a.
Now, When T1 is partially on, it has the fully on T2 in its drain connection. However, when you look at the general characteristics of FETs, you'll see that the drain current saturates when the drain voltage gets to a certain level -- basically meaning that further changes in drain voltage (e.g. from a R in series with the drain) have no effect. What this means is that T2's impact on T1 is smaller than T1's impact on T2, and this is what gives the asymmetry in the curves.
Geerally, this also means that the speed of NAND gate is different for the A and B inputs.
If you needed a perfectly symmetrical characteristic, you could add another copy of T1 & T2, but interchanged and still connected between Y and GND.
Best Answer
This is a homework problem, right?
First of all check whether transistor conduct.
If any of them is in cut-off, then the solution is very simple, right? If both are not in cut-off then we proceed.
You got two separate transistors. This means that you can write two separate current equations. This complicates by the fact that MOSFETs have different equations for "linear" and "saturation" modes of operation. There are four possible combinations for modes of PMOS-NMOS: linear-linear, linear-saturation, saturation-linear, saturation-saturation. You'll need to guess here and check if your guess works - if it doesn't, then you'll get unsolvable equations. In this case you simply check the other combinations. However, just by inspection of the circuit you may be able to eliminate some of the possibilities.
What the unknowns are in these equations? Hint: there are up to four of them (currents, voltages).
You can't solve for four unknowns having just two equations. Too bad. But if you can relate some of the unknowns to each other, you may be able to reduce their number. Try to see what constraints are imposed by the schematic (current relations, voltage relations, ...).
The combination of modes which provides you with a solution for \$V_d\$ is the answer (together with the solution itself).