Different voltage characteristics of CMOS NAND gate for different connections

The short answer is that you don't need 4 terminal FETs to build CMOS logic.

Some Background:

In a simple CMOS process, (P-type Wafer, N-Wells) the substrate contact is directly connected to the conductive wafer. This means that the body terminal of all NFETs are basically shorted together. A similar effect happens with the PFETs, although it isn't as absolute. They aren't shorted together to improve performance, but because it is cheaper and easier to manufacture.

This brings up a question: If we had to tie the body terminal of all NFET devices together, what voltage would we like it to be? For NFETs, the body-source and body-drain connections normally look like reverse-biased diodes. In order to maintain these diodes reverse-biased, the body voltage must be less than \$V_D \mbox{ or } V_S + 0.6\mbox{ Volts}\$. Typically this is done by tying the substrate/body to the most negative voltage present in the system. In digital systems, this is usually ground \$V_{SS}\$. The body terminal of PFETs is typically tied to the most positive voltage, or \$V_{DD}\$ for similar reasons.

For 3-terminal FETs, where the source and body have been internally shorted, the internal diodes will never be forward-biased if the source is always at a lower voltage than the drain. If you are stuck with 4-terminal transistors building discrete gates, it will work with the bodies connected to \$V_{SS}\$ and \$V_{DD}\$, and it will also work with the body shorted to the source.

As specified in comments, it is very likely that you are experiencing excessive loss in your cables. If you are using very long wire or wire of a too small gage, you are actually getting such an equivalent circuit:

^{simulate this circuit – Schematic created using CircuitLab}

Where the vertical resistors are the "computers" modeled as loads and the horizontal resistor are losses in the wire.

The resistor values are arbitrary, but a too small wire may cause the assertion of having a negligible resistance to be false. You can see on AWG page on Wikipédia the resistance of a cooper wire per meter as a result of it gage (diameter). You have to consider that the higher the current, the higher the resistance.

In order to solve your problem it is you case, you have to: 1) Use larger wire (smaller gage); 2) Use shorter wire (if possible); 3) Avoid daisy chaining your boards, as the first wire will have a larger amount of current flowing that the last one, resulting in larger losses.

You should prefer a star configuration:

^{simulate this circuit}

so that you have a different wire starting from your source to each of your board instead of a wire running from power supply to first board, then from first board to second one and so on. Same thing applies to your return path (ground).

You may or may not be able to apply all of the previous advices depending on your setup, though.