Code to add two 4bit numbers in verilog doesn’t work

fpgahdlintel-fpgaverilog

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem…

module part2(SW, LEDG, LEDR);

    input [17:0] SW;
    output [17:0] LEDR;
    output [4:0] LEDG;

    //Red lights for each one
    assign LEDR[17:0] = SW[17:0];

    //Wires between adders.
    wire carry[2:0];

    //Add the first digits of A and B
    full_adder F0(SW[4], SW[0], SW[8], LEDG[0], carry[0]);
    //Add the second digits of A and B
    full_adder F1(SW[3], SW[1], carry[0], LEDG[1], carry[1]);
    //Add the third digits of A and B
    full_adder F2(SW[6], SW[2], carry[1], LEDG[2], carry[2]);
    //Add the last digits of A and B
    full_adder F3(SW[7], SW[3], carry[2], LEDG[3], LEDG[4]);

    endmodule

module full_adder(A, B, CI, S, CO);

    input A, B, CI;
    output S, CO;

    //Sum
    assign S = A ^ B ^ CI;

    //Carry out
    assign CO = (A & B) | (CI & A) | (CI & B);

endmodule

It seems to work for most cases but look what happens with 1 and 10:

enter image description here

Best Answer

Typo in your code:

full_adder F1(SW[3], SW[1], carry[0], LEDG[1], carry[1]);

should instead be

full_adder F1(SW[5], SW[1], carry[0], LEDG[1], carry[1]);

Related Solutions

Electronic – Verilog: Check for two negedges in always block

The always@ is a sensitivity list and generally not a checking list i.e. it doesn't work as an if-else block.

Instead, it indicates when the register/latch specified in the block needs to change states, typically on a clock edge (register) or level change (latch).

If you're trying to detect an edge on an input, such as for an interrupt detection, the recommended way is to synchronise the edge to an internal shift register.

It could be as simple as this:

reg [1:0] det_edge;
wire sig_edge;
assign sig_edge = (det_edge == 2'b10);
always @(posedge clk)
  begin
    det_edge <= {det_edge[0], input};
  end

Then, you can do whatever you want with the edge signal, possibly as an enable signal to a state machine or other block that does something with your device (such as flagging the interrupt).

So, for your application, you may want to do the above twice and then use the two edge detect signals to control some other device/block.

The key point to remember with all HDL work is that HDL stands for Hardware Description Language. It is a replacement for schematics, not software.

For starters, I would recommend starting with the hardware and then translate that into code i.e. draw the schematic and then write the HDL that describes that circuit schematic.

Electronic – Why does this Verilog code produce no output on the FPGA

You do not drive LEDR output at all. You need an assignment like:

assign LEDR = M;

You probably wanted to achieve that by assigning LEDR[3:0] to M (i.e. assign M = LEDR[3:0]), but this two assignments are not equivalent in Verilog.

Best Answer

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Electronic – Verilog: Check for two negedges in always block

Electronic – Why does this Verilog code produce no output on the FPGA

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