Electronic – Verilog: Check for two negedges in always block

hdlintel-fpgaverilog

i try to do something like this:

always @ (negedge speed_dec or negedge speed_inc)
 begin
  do something
 end

This doesn't work as checking for 2 negative edges is to demanding and results in only checking for the clock.

I tried do do the check manually:

    reg old_key0;
always @ (KEY[0])
begin
    if(KEY[0] == 1  & old_key0 == 0)
            do something
    old_key0 = KEY[0];
    end

But now it completely stops working. Can anyone spot the error?

Best Answer

The always@ is a sensitivity list and generally not a checking list i.e. it doesn't work as an if-else block.

Instead, it indicates when the register/latch specified in the block needs to change states, typically on a clock edge (register) or level change (latch).

If you're trying to detect an edge on an input, such as for an interrupt detection, the recommended way is to synchronise the edge to an internal shift register.

It could be as simple as this:

reg [1:0] det_edge;
wire sig_edge;
assign sig_edge = (det_edge == 2'b10);
always @(posedge clk)
  begin
    det_edge <= {det_edge[0], input};
  end

Then, you can do whatever you want with the edge signal, possibly as an enable signal to a state machine or other block that does something with your device (such as flagging the interrupt).

So, for your application, you may want to do the above twice and then use the two edge detect signals to control some other device/block.

The key point to remember with all HDL work is that HDL stands for Hardware Description Language. It is a replacement for schematics, not software.

For starters, I would recommend starting with the hardware and then translate that into code i.e. draw the schematic and then write the HDL that describes that circuit schematic.

Related Solutions

Electronic – Verilog: Break an always block

Yes, you should name your begin-end block and then use disable statement like this:

always @(posedge clk_i or posedge rst_i) begin : block_to_disable
  if(rst_i) begin
    // Do stuff
    disable block_to_disable;
  end

  // Do stuff
end

Though, this is probably non-synthesizable, so you can do such tricks only in simulation (testbenches, etc.).

Electronic – Verilog always block w/o posedge or negedge

Not sure why it would trigger on data_in when written like that unless your synthesising it and simulating at gate level.

always @(posedge clk) in RTL maps to a flip-flop.

always @* in RTL maps to combinatorial logic.

The @* is an auto completed sensitivity list based on any signal which can effect an output (left hand side of =).

Your use of manually specifying a sensitivity list which is not used, to create an output value is not valid for synthesis. As it does not map to hardware.

NB: you should only use <= inside always @posedge blocks (when implying flip-flops) other wise use =.

May be create an edge detection circuit which can be used as an enable for a clocked system.

//Capture Previous trigger values
reg [1:0] trigger_d;
always @(posedge clk) begin
  trigger_d = {trigger_d[0], trigger};
end

reg trigger_toggle;
always @* begin
  //Bitwise XOR reduction operator creates pos & neg edge detect.
  trigger_toggle = ^trigger_d; 
end

always @(posedge clk) begin
  if (trigger_toggle) begin
    data_out <= data_in;  
  end
end

Follow up to question posted in comment for system without dedicated clock:

 logic pos_enable =1'b0;
 logic neg_enable =1'b0;
 always @(posedge trigger) begin
    data_1     <= data_in;  
    pos_enable <= ~pos_enable;
 end

 always @(negedge trigger) begin
    data_2     <= data_in;  
    neg_enable <= ~neg_enable:
 end

 wire sel = pos_enable ^ neg_enable;
 always @* begin
  if (sel) begin
   data_out = data_1;
  end
  else begin
   data_out = data_2;
  end
 end

Best Answer

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Electronic – Verilog: Break an always block

Electronic – Verilog always block w/o posedge or negedge

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