Electronic – Verilog: Check, if a signal is 100 ticks active

hdlverilog

I have one input and one output. And I want to turn the output to 1, if the input was 100 ticks active (100 cycles). 

module check_100(
   input wire clock,
   input wire reset,
   input wire in_a,
   output reg out_a);  

reg[10:0] counter;  

always @(posedge clock) begin
    counter <= counter + 1;
    if(in_a && (counter == 100)) begin
        out_a <= 1;
    end
end

But it doesn't seem to work properly.
Is this a good way to check, whether a signal is 100 ticks/cycles active or not?

Thank you! 🙂

Best Answer

1) You need to increment your counter whenever the input is high (which you do)
2) You need to reset your counter whenever the input is low (which you don't)
3) You need to stop counting after counted to 100 (in case you want the output remain high). It will actually remain high in your case, but only because you are not doing the (2).

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