Cyclone V LVTTL GPIO Termination

cyclonefpgaintel-fpga

On the DE1-SoC (from Terasic) schematic, I found 47 Ohm series resistors connected to GPIOs, they are using 3.3V VCCIO.
The cyclone V datasheet show that no external termination is required as shown in the attached picture.
What will happen if we don't use those resistors, as I found a document for cyclone III and IV interface with 3.3 LVTTL and LVCMOS but didn't found such guide for cyclone V??enter image description here

Best Answer

I found 47 Ohm series resistors connected to GPIOs, they are using 3.3V VCCIO

There are two reasons that I know of for putting series resistors in line with GPIO pins: -

  • Generally the cyclone family (that I've used) are very unforgiving of signals that may exceed 3.7 volts and the current limiting resistor is almost always a good idea. I've seen forums where Altera folk do recommend them on the basis that overshoot and ringing can exceed the 3V7 and cause the device to latch-up and possibly fail.
  • The second reason is when driving data - it acts as a termination resistor at the sending end of the data and prevents sustained corrupting reflections when the receiving end is open circuit.
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