Floorplanning is the step, in which functional blocks are allocated on chip area and total chip area, pins location are finalized.
Now what is the difference in Floorplanning for FPGA, ASIC and Gate Arrays?
I believe, FPGA & Gate Array both do not require floorplanning.
Kindly comment on my view.
Best Answer
Well the difference is that FPGAs and Gate Arrays do have already existing physical design. In some cases you don't bother to do floorplan for FPGAs.
Imagine that you need to use a RAM in your design. Most of the FPGAs have their dedicated SRAM, so you can assign your RAM to it or just use many cells to do the same job.