The memory is addressed using the word lines, and data is transferred into or out of the array using the bit lines.
The word lines are driven from a decoder whose input is the address bus. For any particular binary address, exactly one word line is activated. This turns on all of the pass transistors for one complete row of memory cells, connecting each pair of cross-connected inverters to its pair of bit lines. All of the other rows in the memory array are disconnected from the bit lines and do not participate in the read or write cycle.
When reading a cell, the inverters drive the bit lines — one high and one low — and circuitry not shown compares the voltages on the two bit lines and decides whether the bit is a zero or a one. The bits obtained in this way are grouped together to form a "word" of data, which is then passed to whatever external logic (CPU, video controller, or anything else) that might be connected to the data bus.
When writing a cell, another set of circuitry, also not shown, drives the bit lines — again, one high and one low for each cell. The key here is that the write driver is stronger than the inverters in the memory cell, and can impose a new state on the memory cell regardless of what its previous state might have been.
At the end of the cycle, the word line is deactivated and the cells retain their state.
When you apply a voltage to the gate of an NMOS FET that is greater than the threshold voltage \$V_{t}\$, a channel of electrons is formed under the gate. That channel connects the drain and source so that when you apply a voltage \$ V_{ds}\$, a current flows from between these terminals. In this mode, the MOSFET behaves almost like a resistor, so the current flow depends (although not linearly) on \$V_{ds}\$, but the current will also increase with the gate-source voltage \$V_{gs}\$ because increasing this makes the channel deeper, reducing its resistance. That explains the first part of the curve (active or triode).
However, the electric field near the drain depends not just on \$V_{gs}\$ but also on \$V_{ds}\$. Once \$V_{ds} = V_{gs} - V_{t}\$ (called \$V_{ds,sat}\$) the electric field is cancelled near drain and the channel becomes shorter, no longer reaching the drain, leaving a depletion region between the end of the channel and the drain. Any further increase in \$V_{ds}\$ is dropped across this depletion region so the voltage across the channel stays constant at \$V_{ds,sat}\$ and the current flow is also constant. That is the second region of the curve (saturation).
The explanation of the saturation region above would suggest that FET current is constant with \$V_{ds}\$ in the saturation region. Obviously, from the current-voltage curves we can see that this is not the case, and actually the current slowly rises. This is due to an effect called channel length modulation. As \$V_{ds}\$ continues to increase, it cancels the inverted channel even further from the drain, leading to the channel shortening. This reduces the channel resistance (resistance is proportional to length) leading to higher current flow.
There are obviously a lot of second order effects not covered here, but those are the basics!
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I find out myself that the answer to this question is sometimes wiring gates may be troublesome because of low space. Feedthrough helps here to wire a way out through the gate bypassing it, and connecting to nothing in the gate.