Digital PLL behaviour when signals start off at the same frequency but out of phase

IMPORTANT: the transfer function is an abstraction that tells basically what is the difference between the output (generally speaking) and the input (same as before); it's often used with voltages, but you can use what you want (also ice cream / fruit).

Then, just use the definition: as a Phase-Locked Loop (PLL)...

is a control system that generates an output signal whose phase is related to the phase of an input "reference" signal

...that ratio tells you what will be the phase of the output signal given the phase of the input signal.

The phase is well explained in the race car analogy: if you consider a sinusoidal signal as a dot going around in the euclidean circumference (counter-clockwise), the phase is the difference (in radians) between two signals (two points) in this circumference; or, for a signal, the distance from the 0 (rightmost point) of that circumference. In a more concrete way, is the "time" that has passed since when the signal has been the last time at value 0 while raising.

Since PLLs are circuits that try to synchronize clocks or signals in general, the phase is a good indicator of how much these signals are synchronized.

In most cases, the best way to tell if the frequency of the feedback waveform precisely matches the frequency of reference waveform is to observe whether the two waveforms maintain a fixed phase relationship. If the frequency of the feedback waveform is slightly higher than that of the reference wave, its phase will to lead that of the reference wave form by an increasing amount each cycle. Likewise if its frequency is lower than the reference, its phase will lag each cycle. If the reference waveform is reasonably stable, trying to maintain a phase lock will yield a very stable frequency lock.

There are times when maintaining a phase lock is difficult or counter-productive, such as if one needs to generate a stable frequency whose long-term average matches that of a "warbling" reference. In that case, the fact that a frequency-locked loop wouldn't track the reference frequency as tightly as a phase-locked loop would not be a disadvantage, since the whole purpose of the loop in that case would be to avoid having the warbling in the reference passed through to the output. In general, though, the tighter response of phase-locked loops is preferable to the looser response of frequency-locked loops.