multisimnoisesimulation
I just created a circuit with AD620 in-amp and I'm worried that there is not enough noise.
I wonder if Multisim simulates advanced op-amp/in-amp properties, like input noise and such?
I mean, if I pick medium noise op-amp with 10nV/rt(Hz) – does it produce noise like this?
It's not the same circuit on the emitter. You've got a 1k pot in series with a 1k resistor and the pot wiper connects to a grounding capacitor. You've also got a 10pF cap where it is 100nF in LTSpice.
I'm not saying any of these matter but you can't possibly make comparisons with these glaring disparities.
EDIT
Following comments from the OP, the problem I think arises from the new "intended" operating frequency of the circuit (he uses a 10pF cap on the multisim circuit to set the resonant frequency whilst the LTSpice circuit has 100nF). Added to this is the lack of emitter capacitor - the multisim circuit shows it connected via the wiper of a pot set midway and this will drastically reduce the gain and prevent or delay oscillation. Remember that the collector has to generate enough signal to drive the 10nF capacitor (C3) and at a much higher frequency this 10nF (via C5, 1uF) will probably look like a short circuit - the gain of the transistor has to be greater than 1 for it to begin oscillation and with no directly connected emitter capacitor and a 10nF effectively connected to the collector I think the gain will be less than unity.
I'm not totally familiar with this type of Colpitts oscillator but it seems to me that the LTSpice circuit should oscillate at about 41kHz whereas the MS circuit should operate at about 4.1MHz - this isn't going to happen with a 10pF - its reactance at 4.1MHz will be nearly 4 kohms and this will get "battered" by R1 and R2 in the imedance versus resistance race. Do the sensible thing and start with the same circuit. On the LT circuit, the 100nF will have an impedance of about 40 ohms at 41kHz and therefore not be hardly affected by R1 and R2.
As already mentioned, some bias on the input would be an idea if you are only using a single supply - half the supply voltage supplied through resistors with a parallel value of > 10x the piezo impedance. You also need the bias voltage at the base of the Rf/Rg resistors then. Due to the high impedances involved, you will have to be careful with layout, wire lengths, etc.
As for the offset, you can setup an adjustment pot that injects some current into the negative input to counteract this (and/or get a really low offset opamp - you can get FET trimmed opamps with as low as 100uV offset)
Something like this (some parts left out such as caps, etc) I set the opamp up with 6mV offset, you can see the difference in the simulation:
Sim without adjustment:
Sim with adjustment:
Best Answer
10uV/rt(Hz) is a really noisy op-amp. Most/average ones are about 50nV/rt(Hz).
If you are unsure then look for noise on your transient analysis screen - I'm presuming (not having used Multisim) that you can adjust the transient analysis screen so that the Y axis is just a few micro-volts top to bottom?
Another way around this is to approximately calculate what the noise amplitude might be at the inputs and add a voltage source that generates noise or even a sinewave. For instance if you have 100kHz bandwidth and the op-amp noise is 10nV/rt(Hz) then the equivalent input RMS noise voltage will be 3.16 uV. If you multiplied this by 6.6 you get a decent representation of p-p noise. Next, set your added voltage source to be this amplitude.