Electronic – Unwanted noise/oscillations on op amp output


I am working on a piezo vibration voltage amplifier circuit. The working schematic is attached below. From a 9V battery I am using a 7805 to provide 5V to both my single supply op amp and the 5V power connection on my contact-mic style piezo.

Piezo vibration sensor circuit

I have tried this circuit with several different high impedance JFET op amps. The current setup in question uses a an LMC660CN. It can be used from a single supply, swing rail-to-rail, has 126 dB gain (I believe this to be well over 100,000 V/V gain), 6mV input offset voltage, and input bias current 2pA.

When I power the circuit, Vout initially goes low. When I turn the Rf pot up to about 100k, and the gain is about 1000, the circuit is fairly sensitive, and responds as expected to vibrations I make on my table. I need a high gain to pick up some very, very small vibrations.

If I let the circuit sit for about 30 sec, oscillations will start to occur on the output, between about 0 and 800mV, and sometimes a DC bias appears, and it oscillates in this range about ~400mV.

I have read a lot about oscillating op amps, and I have consulted the datasheet on this chip which proposes adding a 10 pF cap and 100 ohm series R in parallel with Rf. In practice, I found a slightly different setup to work better, as pictured on my schematic. I found that placing an 0.01uF ceramic cap in parallel reduced noise on the output significantly.

In one experiment, I have found:

Gain: 1000 (Rf = 100000, R1 = 100)
Without attempting to make vibrations, U3 Piezo signal node has noise on it, peaking at about +/-16mV
v+ and v- inputs on the op amp have about +/-32mV
The +5V node is a very steady 5V, but the ground has about +/- 38mV noise on it; its noise peaks appear to be random, from what I can tell on my oscilloscope
If I ground the v+ input, the output of the op amp is 1.32V, and changes with adjustments to Rf

Two questions:

  1. how can I further reduce the oscillations or noise on the op ampoutput?
  2. how can I avoid Rf adding DC bias to the output?

Maybe the issue to question #1 is simply the input offset voltage — the datasheet says that input offset voltage is 6mV. If I always have a minimum of 6mV on the v+ input, a gain of 1000 will output 6V. But then, how could this op amp be usable at high gains? (Or any op amp for that matter, since it seems that 6mV is a low value for input offset voltage.)

Thank you for your thoughts.

I have also read this forum, and found the discussion useful about power supplies creating oscillations on the op amp output. I am going to continue to think about some of th
Op amp picks up power rail oscillations from boost conveter

Best Answer

As already mentioned, some bias on the input would be an idea if you are only using a single supply - half the supply voltage supplied through resistors with a parallel value of > 10x the piezo impedance. You also need the bias voltage at the base of the Rf/Rg resistors then. Due to the high impedances involved, you will have to be careful with layout, wire lengths, etc.

As for the offset, you can setup an adjustment pot that injects some current into the negative input to counteract this (and/or get a really low offset opamp - you can get FET trimmed opamps with as low as 100uV offset)

Something like this (some parts left out such as caps, etc) I set the opamp up with 6mV offset, you can see the difference in the simulation:

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Sim without adjustment:

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Sim with adjustment:

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