Electrical – 1 Bit Register out of D-type Flip-Flop

It's obviously just a start, but if that is your first layout attempt it isn't so bad. You're obviously missing lots of details like bulk contacts, labels for your rails, labels on your intermediate signals (Inp) and ports so you can instantiate this at a higher level. I would use a transmission gate rather than just a NMOS pass gate into the bus holder circuits. It gives a larger control range and balances out the leakage current into the storage node(s) (gate capacitance of the inverter). It might be easier to put a simple feedback inverter (bigger L to be weaker drive) to have an actual static bus holder like design to be more robust.

In general a dynamic circuit is something should be clocked for most of it's oppertion, it sounds like you're looking at more of a latching operation so I'd recommend going to a static configuration.

No, your circuit is still a edge-triggered circuit. The pairs NAND1+NAND2 and NAND3+NAND4 lock the state of D when the clock rises from to low to high. Changing D when the clock is high (after the rising edge) does not affect the output.

Let's start with Clk = 0, then is S=1 and R=1.

Now let D=0 during the rising edge of the clock:

• The output of NAND4 will be high.
• The output of NAND3 will be low, because S is still high, thus R=0 => Q=0.
• The output of NAND1 is low.
• The output of NAND2 is high, thus S is high, and R keeps low.

The output of NAND4 will be kept high until the clock is low again because the input connected to R is low regardless of any change on D (after the rising edge).

Please note that the functionality of this circuit relies on the propagation delay of the gates.