Electrical – 5V PWM 0-100% duty cycle output should generate 0-100mV

dacpwm

The project I am attempting is:

Arduino UNO receiving a data record from a battery data logger
one particular value (State of Charge) is extracted
and sent to a PWM output
going through a low pass RC filter
into an OpAmp (LM324) to provide a clean DC output
the output voltage should range from 0-100mV

The PVM frequency is ~480Hz (Arduino Uno); the 2 RC filter are 330R/10uF

I need help with the circuit design past the second RC filter.

This is what I started out with:

_{(source: grenkowitz.net)}

Which morphed into this (and seems flawed/suspicious to me):

_{(source: grenkowitz.net)}

But, I do not reach the 100mV at 100%, and the output is a bit spiky; assuming there needs to be another RC filter of sort.

_{(source: grenkowitz.net)}

The circuit does not need to be responsive, because the duty cycle, thus the mV out increments slowly in 0.5mV steps over hours, and decrements over hours.

[Addition 2016-07-10 0905Z]

Thank you for your responses.

It looks like I am a bit in over my head… not really understanding OpAmps…
I have now taken a slightly different approach, and added a voltage divider on the input signal of %v to drop to .1V and since reaction time does not matter, put a 100uF cap in… then the 2 RC filters into the OpAmp; sorry for the for the Vcc for the OpAmp; now corrected to 5V.

The simulated output is 33-98mV. But I am not sure, how to configure the OpAmp to get a Voltage (as precise as possible) mathing the 0-256 step, 8bit, 0-100% duty cycle of the input.

Here the latest design:

_{(source: grenkowitz.net)}

Best Answer

If you are going to use an op-amp you might as well implement a unity gain sallen key 2nd order low pass filter: -

This will overcome the problem of the first low pass fitler being hampered by the input impedance of the 2nd low pass filter.

You can use this calculator from Okawa Electronic Design to plug in values but I would go for two 1k resistors with C1 at 10uF and C2 a bit smaller, maybe 2.2 uF.

You don't say in your question what the PWM amplitude is but, adding a resistor from the junction of R1 and R2 to ground can produce the required attenuation but the parallel combination of R1 and that extra resistor is the value of R1 to be used in the calculator.

In your 2nd schematic I have no idea why you are attaching the op-amp power to the input voltage waveform. Recipe for rubbish is my thinking. It may look like it's working in a sim but it won't work in practise because, in practise, you need nominally a 10 nF or 100 nF op-amp power-rail decoupler to avoid op-amp mis-workings.

Related Solutions

Electronic – Need help with PIC16F887 PWM output

This is a project in other compiler (MPASM) and other PIC16, but it could help you, note the configuration of the register. The next code is used to control the speed of a motor using a H-bridge, I hope that it works for you:

`   ;use of the CCP module to control motor speed using PWM 
           include p16F877A.inc `

`cntr equ 20
cntr1 equ 21 `


` __CONFIG _RC_OSC & _CP_OFF & _WDT_OFF 
               org 00
             goto start
               org 04
             goto ISR
               org 06
;main program************************************* 
start       bsf STATUS, RP0
            bcf STATUS, RP1 ; select bank 1
            movlw 00
            movwf TRISC 
            movlw B'11111111'
            movwf TRISB
            movwf PR2 ; 255 to PR2
            bcf OPTION_REG, 7 ; active pull-up
            bcf STATUS, RP0 ; select bank 0
            movlw 00
            movwf PORTC
            movlw B'00001100' ; enable PWM
            movwf CCP1CON
            movlw D'128'
            movwf CCPR1 ; 50% duty cycle(motor off)
            bsf T2CON, TMR2ON ; shoot tmr2 without post nor preescale 
            bsf T2CON, T2CKPS1 ; prescaler in 16
            movlw B'10001000' ; INTCON pattern
            movwf INTCON
            goto $
;*************************************************
;SUBROUTINE DELAY*********************************
;*************************************************
delay       movlw D'255'
            movwf cntr
     del1   movlw D'10'
            movwf cntr1
     del    decfsz cntr1
            goto del  
            decfsz cntr
            goto del1
            return
;************************************************`

`;************************************************* 
;INTERRUPT SERVICE ROUTINE************************
;************************************************* 
ISR         btfss PORTB, RB4
            goto incSpeed
            btfss PORTB, RB5
            goto decSpeed
            goto exit`

`incSpeed    movlw D'255'
            xorwf CCPR1, W
            btfsc STATUS, Z ;test increment limit
            goto exit     
            call delay
            movlw D'1'
            addwf CCPR1, F
            btfss PORTB, RB4
            goto incSpeed
            goto exit`

`decSpeed    movlw 0
            xorwf CCPR1, W
            btfsc STATUS, Z ;test decrement limit
            goto exit     
            call delay
            movlw D'1'
            subwf CCPR1, F
            btfss PORTB, RB5
            goto decSpeed
            goto exit`

`exit        bcf INTCON, RBIF
            retfie 
;********************************************  `            
           ` end `

I suggest programming in C compiler

look at the hardw(ISIS PROTEUS): enter image description here

Electronic – PWM DAC Filter explanation

From the schematics given in figure1 and results in figure2, it is clear that PT0 is the PWM signal to be recovered. What is PT1?

It is a separate sample-hold control signal. It needs to have the same period as PT0, but it needs to have a fixed (50%) duty cycle and its rising edge must coincide with the falling edge of PT0.

Also, why does the author say that this DAC settling will take 0.1sec,

Actually, he says 0.01 sec, which is the PWM period he's using as an example (100 Hz from a 16-bit counter). If your PWM is at 10 kHz, you need to adjust R1 and/or C1 so that T2 is equal to 100 µs, and you will get one-cycle settling as well.

The chip used for analog switching is CD4053. This chip selection inputs S1, S2, S3 are active high, but the schematic in figure1 shows these inputs to be active low. Can we simply swap the signal inputs and achieve the same result?

Yes.

Best Answer

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Electronic – Need help with PIC16F887 PWM output

Electronic – PWM DAC Filter explanation

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