I'm just wondering how to access more than 32Kb on a TERASIC DE0 nano. It is based on an Altera Cyclone IV FPGA. https://www.ti.com/lit/ug/tidu737/tidu737.pdf
It has 32Mb DRAM but there are
- 12 address lines
- 2 bank select lines
- 16 data lines
This gives a total of 32Kb. There is a program that is provided called NIOS II which seems to be able to access the memory but there aren't any details about how it works.
So the question is how is the rest of the memory accessed?
Best Answer
The address bus is used for either column or row address, depending on the control signals (RAS/CAS and friends). I don't know which SDRAM chip is on your board, but they are pretty much standardized these days, and differ mostly in timing and maybe in burst options.
Here is a brief overview: Understanding DRAM Operation. Having said that, definitely find the datasheet for your SDRAM chip - it's very informative!
E.g., my DE10 Lite board has this chip: iS42/45S16320F-7TL.
Yours probably has 12-wide row address, 10-wide column address, in total giving \$2^{12+10+2}\$ = 16M words, which for 16-wide data means 32MB (not 32Mb).