Electrical – FPGA, accessing data in RAM

You can use the memory IP cores to create a memory with initial mif content. You can check the IP core user guide for more information.

Another solution is to use VHDL attributes to initialize the content of your variable. You have to be confident that your code is indeed interpreted as a ROM by altera, otherwise the attribute will be ignored. This is the example usage from altera's documentation:

type mem_t is array(0 to 255) of unsigned(7 downto 0);
signal ram : mem_t;
attribute ram_init_file : string;
attribute ram_init_file of ram : signal is "my_init_file.mif";

A third way, which I prefer, is to initialize the memory in VHDL code, for example:

type rom_t is array(0 to 1023) of signed(15 downto 0);

function fill_sin_rom return rom_t is
    variable ret : rom_t;
begin
    for i in ret'range loop
        ret(i) := to_signed(integer((2.0**15 - 1.0)*sin(2.0*MATH_PI*real(i)/1024.0)), 16);
    end loop;
    return ret;
end function fill_sin_rom;

constant sin_rom : rom_t := fill_sin_rom;

This code would be in a package for an architecture declaration sections. It requires use ieee.math_real.all and use ieee.numeric_std.all to work. The advantage of this solution is that it also works in simulation, while the attribute would not.

It's definitely possible to infer block RAMs directly from HDL. Depending on the size and the configuration, the toolchain could place them in block RAM or in distributed RAM.

Here is a very simple verilog example:

module rom
(
    input clk,
    input [3:0] addr,
    output [7:0] data
);

reg [7:0] mem[2**4-1:0];
reg [7:0] output_reg = 8'd0;

initial begin
    mem[4'h0] = 8'h00;
    // ...
    mem[4'hF] = 8'h00;
end

assign data = output_reg;

always @(posedge clk) begin
    output_reg <= mem[addr];
end

endmodule

I have used similar code in both the Xilinx and Altera toolchains, and in general both tools will infer the proper RAM components. This also works for RAMs. And it can be used to store values in a look up table that are computed at synthesis time, though Quartus has historically had some serious issues with this, namely with doing floating point/trig at synthesis time.

Example of precomputing ROM contents in verilog: https://github.com/alexforencich/verilog-dsp/blob/master/rtl/sine_dds_lut.v