Electronic – How to read values from a ROM to control a VGA monitor

fpgaquartusvhdl

first I have to say that I'm still a beginner and learning VHDL so any advice is a lot of help.

What I'm trying to do is control an image in a VGA monitor with an FPGA (Cyclone II), using a .mif file with the bits corresponding to that image and loading them into a ROM, so then I can read the values and show them.

My problem arises when I have to set the ports for the component that I'm using in my code..

architecture aa of VGA is

--some signal declarations here

component RomImage is
port(   address : in std_logic_vector(13 downto 0);
        inclock : in std_logic;
        outclock : in std_logic;
        qrom : out std_logic_vector(23 downto 0)
);
end component;

begin

RomIm : lpm_rom
generic map(lpm_file=>"GameOver.mif",lpm_numwords=>9500, lpm_width=>24, lpm_widthad=>14)
port map(address=>address,inclock=>inclock,outclock=>outclock,q=>qrom);

-- other process and logic

-- Output logic (only red, same for blue and green)

redout(9 downto 7) <= qrom(23 downto 21) when x>=225 and x<=415 and y>=250 and y<=300 else
                      rojo(5 downto 3);

I don't really know what clock I have to use for the inclock and outclock, one of them is to read address and the other for the output q[].
In the design I enter with a 50 MHz clock and then for the VGA clock I divide the frequency to obtain 25 MHz which is the one I need to make the screen work.

I would imagine that the screen sweep has to be synchronized with the frequency at which you have to read the values from the ROM.

Sorry if it's too much code or confusing, I'll try to expand if needed

Best Answer

Been unanswered for a day so let me give it a shot. That ROM is very unusual. I have been an ASIC engineer for more then 25 years and I have never seen a ROM (or memory) with one port and two clocks.
Try to find the model for that ROM or find the specs if it is a FPGA library element. Failing that my best guess would be to use the same clock for both ports. You say you are working on VGA which requires 25 MHz so that is probably your pixel clock. Then you must output three analog signals every clock cycle. (And hsync, vsync + pixel clock). Your 24 bit wide ROM is probably RGB as 888 thus you must clock that ROM out at 25 MHz.
Alternative you could try to use an opposite clock for address and data.

Related Solutions

Electronic – FPGA VGA Buffer. How to read and write

A couple of approaches which may be useful for some styles of display is to divide the display panel into tiles, and

restrict each tile to using a small set of colors, allowing the use of fewer than 8 bits per pixel, or
use a byte or two from each tile to select a location from which to read bitmap data.

The first approach could reduce the rate at which data had to be read from display memory. For example, if one used tiles that were 16x16 and could each have four colors chosen from a set of 256, then without using any extra RAM in the FPGA one could reduce the number of memory reads per 16 pixels to eight (four color values, plus four bytes for the bitmap). If one added 160 bytes' worth of buffering/RAM(*) to the FPGA, one could reduce the number of memory reads per 16 pixels to four, using an extra 160 reads every 16 scan lines to read the next set of tile colors. If one wanted 16 colors per tile, the second approach would require an extra 640 bytes of RAM unless one placed some restrictions on the number of different palettes that could exist on a line.

The second approach would probably increase rather than reduce the total memory bandwidth required to produce a display, but would reduce the amount of memory that would have to be updated to change the display--one could change a byte or two to update an 8x8 or 16x16 area of the screen. Depending upon what you're trying to display, it may be helpful when using this style of approach to use one memory device to hold the tile shapes, and another to hold the tile selection. One might, for example, use a fast 32Kx8 RAM to hold a couple 80x60 tile maps with two bytes per tile. If the FPGA didn't have any buffering, it would have to read one byte every four pixels; even with a 40ns static RAM, that would leave plenty of time for the CPU to update the display (an entire screen would only be 9600 bytes). The memory bandwidth for reading out the tile shapes would be no better than it is now, but that part of memory wouldn't have to be updated.

Incidentally, if one didn't want to add a 32Kx8 RAM but could add add 320 bytes of buffering/RAM(**) to the FPGA, one could use a tile-map approach but have the CPU or DMA feed 160 bytes to the display every 8 scan lines. That would burden the controller somewhat even when nothing on the display was changing, but could simplify the circuitry.

(*) The buffer could be implemented as RAM, or as a sequence of 32 40-bit-long shift registers plus a little control logic.

(**) The buffer could be implemented as two 160-byte RAMs, or as two groups of sixteen 80-bit shift registers.

Electrical – Why can’t I connect a std_logic_vector signal to a port of type signed or unsigned

Although in your example unsigned and signed are both arrays of the same element type std_logic, this is not the same as a subtype. A subtype is when one type is a limited subset of another type, for example:

subtype my_type is std_logic_vector(3 downto 0);
subtype eight_bit_int is integer range 0 to 255;

A feature of a subtype is that it can be automatically converted to and from the parent type, so I can do:

signal a : std_logic_vector(3 downto 0);
signal b : my_type;
signal c : integer;
signal d : eight_bit_int_type;

...

-- These should both work fine
b <= a;
c <= d;

If you want to connect differing types in a port map, you might have to use type casts or type conversions, or both. Using your example entity, you might write something like this:

signal a_actual : std_logic_vector(3 downto 0);
signal b_actual : std_logic_vector(3 downto 0);
signal c_actual : std_logic_vector(3 downto 0);
signal d_actual : std_logic;

...

-- Converting from std_logic_vector to signed or unsigned only requires a cast 
dummy_inst : dummy
port map(
    a => a_actual,
    b => std_logic_vector(b_actual),
    c => std_logic_vector(c_actual),
    d => actual
);

If you wanted to connect an input, for example b to an integer, you would have to use a type conversion and a cast, and the line would look like this:

b => std_logic_vector(to_signed(b_integer, 4)), -- 4 is the length of the port

Best Answer

Related Solutions

Electronic – FPGA VGA Buffer. How to read and write

Electrical – Why can’t I connect a std_logic_vector signal to a port of type signed or unsigned

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