Electrical – altium dashed lines polygon

In the AVR Appnote on hardware design considerations on page 5:

To protect the RESET line further from noise, it is an advantage to connect a capacitor from the RESET pin to ground. This is not directly required since the AVR internally have a low-pass filter to eliminate spikes and noise that could cause reset. Applying an extra capacitor is thus an additional protection. However, note that this capacitor cannot be present if DebugWIRE or PDI is used. If not using High Voltage Programming it is recommended to add an ESD protecting diode from RESET to Vcc, since this is not internally provided due to High Voltage Programming. Alternatively, or in addition, a Zener diode can be used to limit the RESET voltage relative to GND. The Zener diode is highly recommended in noisy environments. The components should be located physically close to the RESET pin of the AVR. Figure 2-1 shows the recommended circuit on the RESET line.

I suggest you try an external capacitor of 0.1uF to ground, and a schottky diode to from RESET to VCC to act as an ESD clamp. Add a 5.1V Zener from RESET to GND, which comes highly recommended in the manufacturer's text.

There are pros and cons.

The advantage of ground on both sides is that you can tie the two ground planes together directly with vias. The advantage ofone side power and the other side ground is that it can provide lower DC voltage drop.

Whatever you do for high speed signals you need to think about your high frequency return paths. The return path should generally be as close as possible to the signal path to minimise inductance. If part of the return path flows through a power plane and part through a ground plane you can tie them together with a capacitor.

A 2 layer board will always be a compromise for high speed because your planes inevitablly end up quite "cut up".

As far as providing power decoupling for the ICs themselves the general rule is that it should be as close to the IC as practical. Your board seems to have a lot of unnessacery space between the capacitors and the IC.