Electrical – Are there better alternatives for these buffers

Looking at the TI datasheet for 74LVC1G125, if you scroll down past the absolute maximum ratings, you'll get to the recommended operating conditions, including a maximum I_OH and I_OL. TI specs 32 mA max for either one, and that's only if you're providing 4.5 - 5 V Vcc. If you're using 3.3 V or lower, the recommended source and sink currents are lower. So I think one part of your question we can answer is, no, the 74LVC1G125 is not a good choice if you need to sink 50 - 100 mA.

To answer the rest of your question probably needs some more information: How fast does the buffer need to switch, what power supply voltages do you have available, is the load resistive, capacitive, or something else?

One option that you could probably get to work very generally is just to use some general-purpose npn transistor on each output. With an appropriate resistor between the CPLD output pin and the transistor base to limit the current, it should be straightforward to achieve 100 mA sink current and output voltage below 0.5 V (depending on the load).

This is more a set of comments than an answer per se, but too long to fit in a comment.

Signal from oscillators: 8Vpp 1~20KHz with an offset of ~10V with a new 9V battery.

So the issue is how to couple this to another stage which can amplify it, but at the same time set an appropriate input voltage DC offset suitable to the next stage.

The obvious solution would be to use any amplifier design with reasonably high input impedance, and AC couple to it via a capacitor, so for example a cap from OSC1 to R8.

"The main problem is, on Q1 base, where the signals meet, there's no signal." Whatever voltage signal is at Q1 base will be quite small because the impedance at Q1 base will be small compared to the 1 Meg input resistors. (Especially for frequencies above the knee of the R5-C7 highpass filter.)

So the voltages at Q1 base may well be only 1/100 or 1/1000 of the signals into R8 and R9. In any case what you are more concerned with is the AC currents through R8 and R9 (and thence into Q1-base).

And probably also of concern is the DC voltage at Q1-base -- is it in a sensible range to bias Q1 to operate in it's active range, say with 3 to 4 V DC at Q1 collector? Since you have a 100k collector resistor on Q1, that suggests you are expecting a DC Ic of around 0.03mA to 0.04mA, and thus a DC voltage of rather precisely 0.03V-0.04V across R5 (and not, for example, 0.08V), but there's nothing to set a suitable voltage on Q1-base to make that happen so far as I can see.

Finally, what is the role of C9, 10nF? In parallel with R11 that appears to create a filter that will attenuate output above 160Hz or so, working to considerably suppress the signals in your range of interest, 1 kHz-20kHz.

It's difficult to say anything about what you wrote after "My mission: be able to make its output signal usable" because you don't show a schematic of what your did and it's hard to guess.

FWIW, if you feed an AC audio signal via a capacitor into a voltage follower (which has a high impedance input, hence shouldn't disrupt the source of the signal), you are going to get an output voltage that follows the input voltage. That's assuming you've set the DC level at the follower input to something reasonable. There's not much that can go wrong there, so we need to see exactly what you did that might have cause this to fail.

Bottom line, it looks like your challenge here may be simply understanding how amplifiers work (either op amps or with discrete transistors) and how to satisfy their input requirements for signal voltage or current, impedance, and DC bias (aka offset). Perhaps reading up on that topic might allow you to navigate more satisfactorily?