Today, I tried to use a ULN2003a darlington array as a buffer for my CPLD's outputs. While it works well, I have a concern. The max. voltage where the Max V is guaranteed to read a low is 0.8V. The darlington array's low level output was 0.7V. I was expecting closer to 0V, but that was not the case.
Because I'm operating near the logic level threshold, I'm not sure if using this darlington array is a good idea. Instead, I'm looking at other dedicated logic level buffers. My current requirements aren't that high – I think about 50 mA to 100 mA per pin would suffice.
I did find a 16-bit tri-state buffer, but I the Enable inputs control 4 outputs at a time. I need a way to control every output. I essentially require a open collector/drain at every output.
With that said, I did the 74LVC1G125. The advantage of this IC is that its max. output voltage for a low is 0.8V. The min. output voltage for a high is 2V. The voltage at which the Max V is guaranteed to read a high is 1.7V. I think this make it a good match.
Now, I haven't really used such a IC before and even though it has two inputs, am I correct in guessing that I could use this just by using the Output Enable (OE)? I could have a pull up resistor at the output, and the A input can be grounded. When the OE is low, the IC tri-states and the resistor pulls up the voltage. When OE is high, the IC outputs A, which was a low. Am I correct in my understanding regarding this or am I missing something?
The downside is that it's just one per package. The other issue is the limiting current of 50mA. SInce this is a absolute rating, I better get too close to this. I would definitely like to have some more legroom for this.
Anyone have any ICs in mind for logic buffering?
Finally, is it wise to have buffers on both ends of a long wire? The length is approximately ~10m. The wire feeds a signal from the output of the CPLD to the input of another CPLD.
EDIT:
The loads are just long (~10m) wires. So, capacitive + resistive load? On the other end, the wires connect to another CPLD. Because the other end has digital inputs, I don't think the load is going to be significant. The frequency of operation is less than 1kHz.
Best Answer
Looking at the TI datasheet for 74LVC1G125, if you scroll down past the absolute maximum ratings, you'll get to the recommended operating conditions, including a maximum I_OH and I_OL. TI specs 32 mA max for either one, and that's only if you're providing 4.5 - 5 V Vcc. If you're using 3.3 V or lower, the recommended source and sink currents are lower. So I think one part of your question we can answer is, no, the 74LVC1G125 is not a good choice if you need to sink 50 - 100 mA.
To answer the rest of your question probably needs some more information: How fast does the buffer need to switch, what power supply voltages do you have available, is the load resistive, capacitive, or something else?
One option that you could probably get to work very generally is just to use some general-purpose npn transistor on each output. With an appropriate resistor between the CPLD output pin and the transistor base to limit the current, it should be straightforward to achieve 100 mA sink current and output voltage below 0.5 V (depending on the load).