Electrical – Asynchronous Active High SET & RESET D-FlipFlop

flipflopverilog

I have two pieces of modules as below, may I ask which one is the right verilog to represent an Asynchronous active high set/reset D-flip flop (Rising clock edge)? Are both of them logically equivalent?

Expected Truth Table for my D-flip Flop

reset  set     clk        q
  1     x       x         0
  0     1       x         1
  0     0   rise-edge     d1
  0     0       0         Qo (previous d1)

First Module dff_async_RS

module dff_async_RS(q, d1, clk, reset, set);
  input d1, clk, set, reset;
  output q;
  reg q_reg;
  always @ (posedge clk)
    begin
    if (reset)
      q_reg <= 1'b0;
    else if (set)
      q_reg <= 1'b1;
    else
      q_reg <= d1;
    end
  assign q = reset ? 1'b0 : (set ? 1'b1 : q_reg);
endmodule

Second Module dff_async

module dff_async(q, d1, clk, reset, set);
  input d1, clk, set, reset;
  output q;
  reg q;
  always @ (posedge clk or posedge set or posedge reset)
    begin
    if (reset)
      q <= 1'b0;
    else if (set)
      q <= 1'b1;
    else
      q <= d1;
    end
endmodule

Best Answer

The problem with your first module is after releasing set or reset back to 0, the q output goes back to the previous q_reg state.

Try it in simulation.

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