I know that assembly costs for a BGA package can run into about 200-300USD for prototypes. But how important is this cost when planning a production run? Is every BGA package soldered onto the PCB actually put into an XRAY and tested? Is there any pictures showing BGA vs TQFP assembly costs for a run of about 10,000 pieces?
Electrical – BGA vs SMD assembly costs
assemblypcb
Related Solutions
I'd like to place these additional CPLDs on a different PCB. This has the advantage that I can simply extend the device when I need. On smaller harnesses, a single 114 test-point PCB will suffice. On larger ones, I can cascade.
There are multiple levels of modularization which you can aim for. Where you want to stop depends on your specific use case. At the most basic level, the hardware must be designed such that you can select the number of modules in use after the design stage. The difficulty of changing the number of modules, space available, desired software complexity (and available space for software, especially on a CPLD) and the system cost will be key factors in your decision.
Hardware
The simplest and cheapest way to do this is to build one PCB, (You don't need multiple PCBs for modular design!) and put footprints for your desired maximum number of CPLDs on the PCB. If you need more IO, you can then solder down another CPLD. Obviously, this isn't something you'd want to do very often.
At the next stage, you'd want to build daughtercards so that you can more easily add and remove modules. You asked:
But what would be the best way to actually connect the PCBs together?
This depends on your system architecture and number of modules. If you know you'll never want more than, say, 3 modules at any one time, just put three connectors on the main board. These can be edge connectors, or stackable connectors, or whatever you like that doesn't require wires. If the number of sub-modules is too large to fit connectors for each on one PCB, then you should consider stacking (if your bus can handle the fanout of your maximum number of modules) or daisy-chaining (if you need to buffer the signal or vertical space is limited) the modules.
Plenty of connectors are designed for this purpose; check the "Board-to-Board" section of your favorite distributor or manufacturer, and many are designed for extremely low crosstalk and high frequency - 500kHz is nothing, unless you're using PTH 0.1" breakaway headers and have fast-changing signals (even then, you're probably OK). Check the mating strength of your connectors just to be sure, but if you only have a few pins, the footprint of your interconnection doesn't carry the stresses well, or the system will be subject to vibration, you'll need standoffs. It's often wise to design the interface in such a way that different modules can be designed to interface with the motherboard in the future. Pins are cheap, give yourself a couple spares just in case!
Software
If your number of modules supports it, you can simply add a slave select line for each module. This isn't really a software solution, but I wanted to mention it.
If you don't mind programming every CPLD differently, you could build the system such that the microcontroller sees it as one giant shift register (which you've suggested). If you added or removed a module, that module's address space would simply be wasted, and extra time would be used transmitting to addresses which don't exist. Each module would need to 'know' its address space, though, which would make programming the complete system a struggle.
A more versatile solution is to use software addressing to access each sub-module. In a 'programming mode' (perhaps a pushbutton on the module, or simply only connecting one at a time), you could assign the CPLD an address. By assigning each CPLD a different address, you could add or remove modules at will, and only have to adjust the activity of the microcontroller (which I presume to be easier to adjust than the CPLD).
My suggestion for this project
If a 324-pin device will solve all your foreseeable use cases, then the single-PCB method should work fine. The multiple-slave-select method would allow you to program all the CPLDs simultaneously with a single programmer. Sorry, but this project as described doesn't seem like a candidate for daughtercards.
There are sockets available for both DIP packages and SMD packages. No matter which direction you take, I would suggest using a socket. That way, if you let the smoke out, replacing the chip doesn't require desoldering and resoldering.
The choice between DIP and SMD is all about what you are more comfortable with. There is typically a larger variety of microcontrollers available in SMD. But they are also more fragile. Especially when used with a socket. If you're taking the chip in and out a lot, you will most likely bend or break some pins. The pins on a DIP are much more forgiving in this respect.
It's rare that you'll find someone taking a chip out of circuit and placing it in an off-board programmer these days. I had to do it with old school PROMs in college. But I haven't done it since. You are much better off having the JTAG on the board itself. @i.amniels mentioned in-circuit debugging being a huge advantage. I will echo that sentiment as it cannot be said enough.
There are many different JTAG connector configurations. The AVR one uses 10 pins. And you really don't have a lot of say in the footprint of the header you can choose. You have to match the pin size and pitch to your JTAGICE. Atmel has a recommendation for the part number to use to interface to the JTAGICE. I would just stick with that.
http://support.atmel.com/bin/customer.exe?=&action=viewKbEntry&id=2
Best Answer
BGAs have superior reflow characteristics as they are pulled onto the pad during reflow (due to surface tension). Due to this effect, the placement accuracy for a BGA is slightly looser than for standard SMD components such as QFP and QFN.
QFP devices will solder wherever they have been placed.
BGAs are not a cure-all, of course; they have their challenges, particularly X-Ray post soldering, but I have had automated X-Ray testing on boards in the past that had a very low error rate.
QFP devices can catch the unwary if the PCB is tested by bed of nails or roving probe: I have seen devices where a pin was clearly not soldered, but the probe pushed it onto the pad, making an electrical contact during automated test only; the board failed a functional test, but as that is further down the process, it becomes more expensive to fix, under some circumstances.
In production, the cost of manufacturing is the cost of a pick and place which should be comparable for QFP and BGA devices on any modern system.