Electrical – Bidirectional assignment in Systemverilog

system-verilogverilog

I need to create mux block that works with inout pins.
My module has n inputs and n outputs, I want to be able to switch
between different outputs.

The problem that I am currently having is that I need to do that with
inout pins. So if my output pin is pulled down, the input pin of the
mux shall see that. This doesn't work with a common assign statement since
it will only write in one direction. I have tried an alias statement, which
works like a bidirectional assign, but I can not combine this with an if statement for the mux.

What I want to do:

alias net_out = (config) ? net1 : net2;

I have created an example on edaplayground

Best Answer

If you are trying to model a bidirectional mux, the tranif primitives might be more appropriate/easier, depending on what your end goal is.

tranif1 #(t_on, t_off) ( a, b, ena);

tranif1 #(1, 1) ( net1, net2, config );

tranif0 #(1, 1) ( net2, net1, config );

Related Solutions

Electronic – Unexpected Verilog warning re FPGA clock assignment

The warning is basically suggesting that you use an explicit clock primitive, which for whatever reason isn't inferred automatically by the tools.

There should be a reference for your particular FPGA that tells what primitives are available. For a Spartan3E, for example, Xilinx UG617 describes the BUFGCE primitive ("Global Clock Buffer with Clock Enable") and shows how to instantiate it. Other vendors will have similar documentation.

Your clock distortion is probably occurring because tristating an output line isn't something that can be done instantly. Whatever is being driven has both inductance and capacitance, so even if the driver could go high-Z in zero real time (which it can't), the driven network will continue to ring for some time. If that's a problem, you would need to find a way to ensure that the clock line is low, and has been for some time, before tristating it. All in all, there is probably a better way to accomplish your goal besides tristating a clock.

Electronic – Birectional I/O pin in verilog

Inouts are actually "wire" so you can't use any procedural/sequential assignments (where the left hand side must be a reg). Generally speaking:

input : internally must always be of type net, externally the inputs can be connected to a variable of type reg or net.
output : internally can be of type net or reg, externally the outputs must be connected to a variable of type net.
inout : internally or externally must always be type net, can only be connected to a variable net type.

A common approach is to have an "enable" signal for the output of your inout, and to drive to high impedance if the output is not enabled. In your case direction is playing that role.

So try this instead:

module test(
    input  clk,      // The standard clock
    input  direction,  // Direction of io, 1 = set output, 0 = read input
    input  data_in,    // Data to send out when direction is 1
    output data_out,   // Result of input pin when direction is 0
    inout  io_port     // The i/o port to send data through
    );

    reg a, b;    

    assign io_port  = direction ? a : 1'bz;
    assign data_out = b;

    always @ (posedge clk)
    begin
       b <= io_port;
       a <= data_in;
    end

endmodule

The hardware corresponding to the above code would look something like this:

enter image description here

Best Answer

Related Solutions

Electronic – Unexpected Verilog warning re FPGA clock assignment

Electronic – Birectional I/O pin in verilog

Related Topic