Electrical – Calculate number of states in edge triggered flip flops

Considering a positive-edge triggered FF followed by a negative-edge triggered FF and 1st FF is triggered at t=0 sec. The triggering edge for 2nd FF will arrive only after \$T_{clk} + T_{skew}\$. But the output of 1st FF takes some time (\$T_{clk\rightarrow Q}\$) to settle to a stable value. Stable value should reach at input to the 2nd FF atleast \$T_{setup}\$ seconds before the triggering edge arrives. ie,

$$\frac{T_{clk}}{2} + T_{skew} > T_{clk\rightarrow Q} + T_{logic,max} + T_{setup} $$ or, $$ T_{logic,max} < \frac{T_{clk}}{2} - T_{clk\rightarrow Q} - T_{setup} + T_{skew}$$

The triggering edge to 2nd FF arrives at \$t = T_{clk} + T_{skew}\$. The next triggering edge for 1st FF will happen at \$t =T_{clk}\$ sec, ie., \$T_{clk}/2-T_{skew}\$ sec after triggering 2nd FF. Hence 2nd FF can have a hold time of \$T_{clk}/2-T_{skew}+ min\ delay\ between\ the\ FF's\$. ie., $$T_{hold} < \frac{T_{clk}}{2} - T_{skew} + T_{clk\rightarrow Q,cd} + T_{logic,min}$$ or, $$ T_{logic,min} > \frac{T_{clk}}{2} + T_{clk\rightarrow Q,cd} + T_{hold} + T_{skew}$$

Where, \$T_{clk\rightarrow Q,cd}\$ is the clock to Q contamination delay defined as time taken to produce the first change in output of the FF after applying clock and \$T_{clk\rightarrow Q}\$ is the time taken to make stable change in the FF output after clock is applied.

You want to generate this sequence right?

For that start with truth table.

 000 --> 00111 
 001 --> 00101
 010 --> 10000 
 011 --> 11011 
 100 --> 00001 
 101 --> 10100 
 110 --> 11100 
 111 --> 11111

First you make 3 bit synchronous counter using D flip-flop. Use counter outputs as input variable for logic circuit to get respective output combination. First draw 3 variable (outputs of counter) K-map for Z1. Find boolean equation for the same. Repeat this for Z2, Z3, Z4 and Z5.

If you need more clarification let me know.