We can only guess since you haven't told us the syntax error, but from the code posted it MIGHT be:
signal data0_sim : std_logic_vector(8-1 downto 0);
data0_sim <= "00001111";
Now there are two things you might be trying to do here:
1) declare a signal and give it an initial value. The correct syntax for that is:
signal data0_sim : std_logic_vector(8-1 downto 0) := "00001111";
Note that the initialiser uses the variable assignment syntax,to indicate that signal assignment semantics (postponed assignment, event generation) don't apply.
2) declare a signal and later, assign it a value.
The correct syntax for that requires more context : declarations and statements occupy two different spaces in a VHDL unit. This follows programming languages such as Ada, but it is rather different from C.
In VHDL, the context may be an entity/architecture such as:
entity demo is
end demo;
architecture test of demo is
-- declaration region : your signals, constants, types etc here
signal data0_sim : std_logic_vector(8-1 downto 0);
begin
-- statement region : your code here
data0_sim <= "00001111";
end test;
Best Answer
Firstly, hex file are text files. Secondly, I have found it easier to write scripts to parse the external files in VHDL, than to use VHDLs limited text processing capabilities.
Another option you have is to use some of the RAM of the FPGA. You can configure the RAM using your hex file. This is perfect if you are testing internal memory.
A cautionary note: text IO is not supported by many IDEs for synthesis, even though it is in the VHDL spec. I once lost a few hours parsing text in VHDL only to find it will not synthesize.
Edit I know this is not an answer to the original question, but I wanted to point out that there are better tools for the task. You can save yourself a lot of headaches by using a parsing library.